公开(公告)号：US08145786B2

公开(公告)日：2012-03-27

申请号：US12245779

申请日：2008-10-06

申请人： Gidon Gershinsky ,  Konstantin Shagin

发明人： Gidon Gershinsky ,  Konstantin Shagin

IPC分类号： G06F15/16 ,  G06F13/12 ,  G06F13/00

CPC分类号： G06F5/14 ,  G06F2205/063 ,  G06F2205/108

摘要： Buffering messages by receiving a message from a messaging client, writing the message to a logically-contiguous write-available region of a message buffer starting at a logically next write-available location within the write-available region, updating a head index to indicate a head boundary between a logically last message in the message buffer and a logically next write-available location in the message buffer, defining a packet including the message within the message buffer, transmitting a packet that includes a logically first message in the message buffer, and updating a tail index to indicate a tail boundary between a new logically last write-available location in the message buffer and a new logically first message in the message buffer.

摘要翻译： 通过从消息传递客户端接收消息来缓冲消息，将消息写入消息缓冲器的逻辑上连续的写可用区域，从写可用区域内的逻辑下一个写可用位置开始，更新头索引以指示 在消息缓冲器中的逻辑上一个消息与消息缓冲器中的逻辑下一个写可用位置之间的头部边界，定义包含消息缓冲器内的消息的分组，在消息缓冲器中发送包括逻辑上第一消息的分组，以及 更新尾部索引以指示消息缓冲器中新的逻辑上一个可写入可用位置与消息缓冲器中新的逻辑上第一个消息之间的尾部边界。

公开(公告)号：US08127074B2

公开(公告)日：2012-02-28

申请号：US12481376

申请日：2009-06-09

申请人： Steven D. Rostedt

发明人： Steven D. Rostedt

IPC分类号： G06F12/00

CPC分类号： G06F11/3636 ,  G06F5/10 ,  G06F11/3648 ,  G06F2205/064 ,  G06F2205/108

摘要： In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page for a reader of the ring buffer, the ring buffer stored in a physical memory device, and swapping, by the processing device, a head page of the ring buffer with the reader page so that the reader page is part of the ring buffer and the head page is no longer attached to the ring buffer.

摘要翻译： 在一个实施例中，公开了一种用于环形缓冲器的读取器页面的机构。 在一个实施例中，用于实现环形缓冲器的读取器页面的方法包括：通过处理设备将与环形缓冲区分开的存储块分配为环形缓冲器的读取器的读取器页面，存储在环形缓冲器中的环形缓冲器 物理存储设备，并且由处理设备交换具有读取器页面的环形缓冲器的头页，使得读取器页面是环形缓冲器的一部分，并且头部页面不再附着到环形缓冲器。

公开(公告)号：US07600143B1

公开(公告)日：2009-10-06

申请号：US10922214

申请日：2004-08-19

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： G06F1/04

CPC分类号： G06F7/06 ,  G06F2205/065 ,  G06F2205/108

摘要： A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.

摘要翻译： 一种方法和装置允许数据以四种传输模式之一穿过高速缓存接口设备。 快速旁路模式在与其接收的相同的主时钟周期内提供接收的高速缓存数据，而慢速旁路模式在随后的主时钟周期内提供接收到的高速缓存数据。 队列模式提供由缓存接口设备使用的可编程延迟量，由此连续队列模式提供先进先出（FIFO）操作以连续检索排队的数据。 另一方面，块队列模式提供了一种使用可编程偏移量来检索排队数据的方法，以便在高速缓存接口数据总线上不需要使用无操作（NoP）时钟周期来实现部分高速缓存行检索。

公开(公告)号：US07272675B1

公开(公告)日：2007-09-18

申请号：US10841865

申请日：2004-05-06

申请人： Somnath Paul ,  Sanjay Rekhi

发明人： Somnath Paul ,  Sanjay Rekhi

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F9/40

CPC分类号： G06F5/10 ,  G06F5/14 ,  G06F2205/061 ,  G06F2205/106 ,  G06F2205/108

摘要： Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

摘要翻译： 公开了一种在用于调度背对背多信道分组片段的存储转发的接口中使用的装置和方法，包括先进先出（FIFO）存储器，FIFO存储器的读指针， 所述读取指针通过每次读取的单位访问和每次读取的单位访问的一小部分以及FIFO存储器的写入指针中的至少一个来增加，所述写入指针通过每次写入的单位访问中的至少一个来增加，以及 每次写入单位访问的一小部分。

公开(公告)号：US20030120842A1

公开(公告)日：2003-06-26

申请号：US10226083

申请日：2002-08-22

发明人： Matthew M. Bace

IPC分类号： G06F003/00

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： A method of processing data includes writing a data block of size m where m is greater than zero into a queue. The method also includes reading a data block of size n where n is greater than zero from the queue and where the size of n is different from the size of m. The queue can be a FIFO queue. The queue can also have a configurable size.

摘要翻译： 处理数据的方法包括将m大于零的大小为m的数据块写入队列。 该方法还包括从队列读取大小为n的数据块，其中n大于零的数据块，其中n的大小与m的大小不同。 队列可以是FIFO队列。 队列也可以具有可配置的大小。

公开(公告)号：US20010018734A1

公开(公告)日：2001-08-30

申请号：US09769322

申请日：2001-01-26

发明人： Kok Tjoan Lie

IPC分类号： G06F015/00

CPC分类号： G06F5/06 ,  G06F2205/108

摘要： Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.

摘要翻译： 公开了一种用于提高其中FIFO（24）被并入上游处理模块（22）和下游处理模块（26）之间的管道中的管道系统的性能的方法和装置（20），每个模块（ 22,26）可访问公共外部存储器（32），这在许多ASIC布置中是典型的。 该方法开始于检测FIFO（24）何时基本上已满，并将命令从上游模块（22）传送到外部存储器（32）。 由下游模块（26）从FIFO（24）和外部存储器（32）中的每一个接收的命令被解释为确定以下命令的源。

公开(公告)号：US06243799B1

公开(公告)日：2001-06-05

申请号：US09130569

申请日：1998-08-07

申请人： Raymond K. Chan ,  Mario F. Au

发明人： Raymond K. Chan ,  Mario F. Au

IPC分类号： G06F1206

CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F2205/108

摘要： A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte: count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading. An arbiter receives the cell available signals, and it generates control signals to select one of the FIFO memory cores. An output selection circuit utilizes the control signals to output data from one of the FIFO memory cores. The FIFO memory device further includes a plurality of output pins that receive the cell available signals and that receive the cell size information.

摘要翻译： 先进先出（FIFO）存储器件包括多个包含多个单元的FIFO存储器核。 可变单元大小电路支持FIFO存储器件中的用户可编程单元尺寸，以允许选择宽范围的单元尺寸。 可变单元大小电路控制对存储器件中的单元的连续访问，并且当字节：count等于单元大小值以初始化用于后续访问操作的电路时，它重置字节计数。 可变小区大小电路还包括预测电路，其指示在实际访问完成之前对小区的访问完成预定数量的计数。 对准电路在存储每个单元的奇数个字节的单元中产生用于写入操作的数据，以补偿每个单元读取操作的两个字节。 每个FIFO存储器核心包括产生单元可用信号以指示相应FIFO存储器核心中的单元是否可用于读取的电路。 仲裁器接收单元可用信号，并产生控制信号以选择一个FIFO存储器内核。 输出选择电路利用控制信号从一个FIFO存储器核心输出数据。 FIFO存储器件还包括多个输出引脚，其接收单元可用信号并接收单元尺寸信息。

公开(公告)号：US6128715A

公开(公告)日：2000-10-03

申请号：US866822

申请日：1997-05-30

申请人： Chi-Lie Wang ,  Ngo Thanh Ho

发明人： Chi-Lie Wang ,  Ngo Thanh Ho

IPC分类号： G06F5/10 ,  G06F5/14 ,  H04L12/56 ,  G06F12/00

CPC分类号： G06F5/14 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9089 ,  G06F2205/102 ,  G06F2205/108

摘要： A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.

摘要翻译： 能够进行异步读写功能的发送分组缓冲器用于从主机接收帧数据并通过网络转发数据。 该设备包括能够独立写入和读取访问的双端口存储器，用于存储到存储器中的位置的地址指针的多个寄存器以及耦合到双端口存储器和多个寄存器的逻辑设备，用于控制将数据下载到 以第一时钟速度存储存储器，并以第二时钟速度从存储器发送数据。 寄存器用于存储存储器地址供逻辑器件参考，数据被分成帧。

公开(公告)号：US06122717A

公开(公告)日：2000-09-19

申请号：US664873

申请日：1996-06-17

申请人： Raymond K. Chan ,  Mario F. Au

发明人： Raymond K. Chan ,  Mario F. Au

IPC分类号： G06F5/00 ,  G06F5/10 ,  G06F12/02

CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F2205/108

摘要： A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading. An arbiter receives the cell available signals, and it generates control signals to select one of the FIFO memory cores. An output selection circuit utilizes the control signals to output data from one of the FIFO memory cores. The FIFO memory device further includes a plurality of output pins that receive the cell available signals and that receive the cell size information.

摘要翻译： 先进先出（FIFO）存储器件包括多个包含多个单元的FIFO存储器核。 可变单元大小电路支持FIFO存储器件中的用户可编程单元尺寸，以允许选择宽范围的单元尺寸。 可变单元大小电路控制对存储器件中的单元的连续访问，并且当字节计数等于单元大小值时，它重置字节计数，以初始化用于后续访问操作的电路。 可变小区大小电路还包括预测电路，其指示在实际访问完成之前对小区的访问完成预定数量的计数。 对准电路在存储每个单元的奇数个字节的单元中产生用于写入操作的数据，以补偿每个单元读取操作的两个字节。 每个FIFO存储器核心包括产生单元可用信号以指示相应FIFO存储器核心中的单元是否可用于读取的电路。 仲裁器接收单元可用信号，并产生控制信号以选择一个FIFO存储器内核。 输出选择电路利用控制信号从一个FIFO存储器核心输出数据。 FIFO存储器件还包括多个输出引脚，其接收单元可用信号并接收单元尺寸信息。

公开(公告)号：US5210829A

公开(公告)日：1993-05-11

申请号：US626793

申请日：1990-12-12

申请人： Haim Bitner

发明人： Haim Bitner

IPC分类号： G06F3/06 ,  G06F5/10 ,  G11B20/10

CPC分类号： G06F5/10 ,  G06F3/0601 ,  G11B20/10 ,  G06F2003/0691 ,  G06F2003/0698 ,  G06F2205/108

摘要： This invention relates to a tape drive with an electronic buffer which temporarily stores data transferred between the host computer and the tape drive's magnetic tape. More specifically, during a write transaction, in which data is transferred by the host computer to the tape drive for storage, the present invention involves the buffer having an adjustable threshold, or "watermark", which must be reached by the data stored in the buffer before the tape drive begins the operation of ramping the tape up to its write velocity so that it can record the data stored in the buffer. To the extent that the rate at which data is sent to the tape drive from the host computer may vary, the adjustment of the watermark by the tape drive is for the purpose of locating the watermark that is optimal for the data input rate at any given point in time. It does so with its chief objective being the maximization of the tape drives availability to accept data from the host computer whenever the host is ready to send data. A secondary objective, however, is to minimize the number of mechanical operations of the tape drive in the interest of decreasing, to the extent possible, the amount of physical wear on the tape and the tape heads. The invention is also implemented in read operations and works in the same basic manner and has the same objectives as discussed in connection with write operations.

摘要翻译： 本发明涉及具有电子缓冲器的磁带驱动器，其临时存储在主计算机和磁带驱动器的磁带之间传送的数据。 更具体地说，在写入事务期间，数据由主计算机传送到磁带驱动器以进行存储，本发明涉及具有可调节阈值或“水印”的缓冲器，其必须由存储在 在磁带驱动器开始将磁带上升到写入速度的操作之前的缓冲器，以便它可以记录存储在缓冲器中的数据。 在数据从主计算机发送到磁带驱动器的速率可能变化的程度上，磁带驱动器对水印的调整是为了定位在任何给定的数据输入速率下最佳的水印 时间点。 它的主要目的是最大化磁带机的可用性，以便在主机准备发送数据时从主机接收数据。 然而，次要目标是尽可能减少带驱动器的机械操作的数量，以尽可能减少带和磁带头上的物理磨损量。 本发明也在读操作中实现并以相同的基本方式工作，并且具有与结合写操作所讨论的相同的目的。