公开(公告)号：US20180349306A1

公开(公告)日：2018-12-06

申请号：US15826138

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： FLORIAN A. AUERNHAMMER ,  DANIEL WIND

IPC: G06F13/24 ,  G06F12/122

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/542 ,  G06F12/122 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2213/2424

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

公开(公告)号：US20180307624A1

公开(公告)日：2018-10-25

申请号：US15494922

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Neta Zmora ,  Eran Ben-Avi

IPC: G06F12/128 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0846

CPC classification number: G06F12/128 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0848 ,  G06F2212/282 ,  G06F2212/621 ,  G06F2212/69 ,  G06N99/005

Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180165221A1

公开(公告)日：2018-06-14

申请号：US15374788

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Fowler

IPC: G06F12/128 ,  G06F12/122

CPC classification number: G06F12/128 ,  G06F12/0888 ,  G06F12/122 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an access request. If the targeted data is found in the cache and the targeted data is of a no allocate data type indicating the targeted data is not expected to be reused, then the targeted data is read from the cache without updating cache replacement policy information for the targeted data responsive to the access. If the lookup results in a miss, to the targeted data is prevented from being allocated in the cache.

公开(公告)号：US09990290B2

公开(公告)日：2018-06-05

申请号：US15485453

申请日：2017-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dean G. Bair ,  Jonathan T. Hsieh ,  Matthew G. Pardini ,  Eugene S. Rotter

IPC: G06F12/0815 ,  G06F12/128 ,  G06F12/0808

CPC classification number: G06F12/0815 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/0808 ,  G06F12/0837 ,  G06F12/0893 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/281 ,  G06F2212/465 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

公开(公告)号：US09965400B2

公开(公告)日：2018-05-08

申请号：US15140500

申请日：2016-04-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/00 ,  G06F12/121 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/121 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/1009 ,  G06F2212/2022 ,  G06F2212/69 ,  G06F2212/70

Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes using a first management mode to manage the rewritable non-volatile memory module after the rewritable non-volatile memory module is powered on; and using a second management mode to manage the rewritable non-volatile memory module if a shut down command is received from a host system, wherein the second management mode is different from the first management mode and the second management mode executes at least one mandatory processing procedure in background.

公开(公告)号：US09965350B2

公开(公告)日：2018-05-08

申请号：US15281690

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Craddock ,  Matthias Klein ,  Eric N. Lais ,  Harry M. Yudenfriend

IPC: G06F11/10 ,  G06F12/126

CPC classification number: G06F11/1004 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1041 ,  G06F2212/40 ,  G06F2212/69 ,  G06F2212/70

Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.

公开(公告)号：US20180101476A1

公开(公告)日：2018-04-12

申请号：US15288792

申请日：2016-10-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BERNARD C. DRERUP ,  RAM RAGHAVAN ,  SAHIL SABHARWAL ,  JEFFREY A. STUECHELI

IPC: G06F12/0864 ,  G06F12/128

CPC classification number: G06F12/0864 ,  G06F12/0833 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  G06F2212/69 ,  G06F2212/70

Abstract: A set-associative cache memory includes a bank of counters including a respective one of a plurality of counters for each cache line stored in a plurality of congruence classes of the cache memory. Prior to receiving a memory access request that maps to a particular congruence class of the cache memory, the cache memory pre-selects a first victim cache line stored in a particular entry of a particular congruence class for eviction based on at least a counter value of the victim cache line. In response to receiving a memory access request that maps to the particular congruence class and that misses, the cache memory evicts the pre-selected first victim cache line from the particular entry, installs a new cache line in the particular entry, and pre-selects a second victim cache line from the particular congruence class based on at least a counter value of the second victim cache line.

公开(公告)号：US09940253B2

公开(公告)日：2018-04-10

申请号：US14939838

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

公开(公告)号：US09940252B2

公开(公告)日：2018-04-10

申请号：US14939762

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

公开(公告)号：US09940249B2

公开(公告)日：2018-04-10

申请号：US14939516

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.