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1.发明申请公开(公告)号：US20180261133A1
公开(公告)日：2018-09-13
申请号：US15762314
申请日：2016-10-11
发明人： Koki HAMADA , Ryo KIKUCHI
IPC分类号： G09C1/00
CPC分类号： G09C1/00 , G06F7/586 , H04L2209/46
摘要： A combination of secure texts of values “a”, “b” and “c” having a relationship c=ab is efficiently generated. A secure text generation part 12 generates secure texts [xi] of xi satisfying xi=f(ki), and secure texts [yi] of yi satisfying yi=g(ki), for i=0, . . . , m. A fragment generation part 13 generates εi decrypted from [xi]−[ai] and ρi decrypted from [yi]−[bi], for i=1, . . . , m, and calculates [ci]+εi[bi]+ρi[ai]+εiρi and generates secure texts [z1], . . . , [zm]; and A random number synthesizing part 14 generates a secure text [z0] using different values k0, . . . , km and secure texts [z1], . . . , [zm].
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公开(公告)号：US09804826B2
公开(公告)日：2017-10-31
申请号：US14562504
申请日：2014-12-05
申请人： NVIDIA Corporation
IPC分类号： G06F7/58
CPC分类号： G06F7/586
摘要： System and method for pseudo-random number generation based on a recursion with significantly increased multithreaded parallelism. A single pseudo-random generator program is assigned with multiple threads to process in parallel. N state elements indexed incrementally are arranged into a matrix comprising x rows, where a respective adjacent pair of state elements in a same column are related by g=(M+j)mod N, wherein j and g represent indexes of the pair of state elements. x can be determined through an modular manipulative inverse of M and N. The matrix can be divided into sections with each section having a number of columns, and each thread is assigned with a section. In this manner, the majority of the requisite interactions among the state elements occur without expensive inter-thread communications, and further each thread may only need to communicate with a single other thread for a small number of times.
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公开(公告)号：US20150012579A1
公开(公告)日：2015-01-08
申请号：US14139832
申请日：2013-12-23
申请人： Hiroshi NAKAZAWA , Naoya NAKAZAWA
发明人： Hiroshi NAKAZAWA , Naoya NAKAZAWA
IPC分类号： G06F7/58
摘要： An invention is presented with new and simple ways of spectral tests applicable to the multiplicative congruential generator (d,z) with any odd modulus d and any multiplier z coprime to d. The invention realizes powerful ways to select multipliers of excellence with greatly improved statistical performances in their generation of uniform and independent random numbers. Related two inventions for new designs of the generator (d,z) are presented at the same time, as strongly facilitative for the application of advocated extended spectral tests, by exploiting specific structures of moduluses formed by two odd-prime-powers so as to realize improved periodic structures that are set conveniently out of tune avoiding harmful resonances.
摘要翻译： 本发明提供了适用于具有任何奇数模数d和任何乘数z互补对d的乘法同余发生器（d，z）的新的和简单的光谱测试方法。 本发明实现了在均匀和独立随机数的产生中大大提高了统计性能的强大方法来选择优秀的乘法器。 对于发电机（d，z）的新设计的两个发明，同时被提出，通过利用由两个奇数次幂形成的模态的具体结构，对于主张的扩展频谱测试的应用是非常有利的，以便 实现改进的周期性结构，其设置方便地避免有害共振。
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公开(公告)号：US20080294707A1
公开(公告)日：2008-11-27
申请号：US12124821
申请日：2008-05-21
申请人： Akira Suzuki , Masayo Shiba , Kohei Seino
发明人： Akira Suzuki , Masayo Shiba , Kohei Seino
CPC分类号： B60R25/20 , B60R25/042 , B60R25/045 , G06F7/586 , G06F7/588 , G07C9/00309 , G07C2009/005 , G07C2009/00761
摘要： A random number generation device including a first random number generation part which generates a new random number based on a random number which was previously generated and which outputs the random number generated by the first random number generation part, the random number generation device includes: a second random number generation part which generates a random number different from the random number generated by the first random number generation part; and an operation part which outputs a random number obtained by a prescribed operation using a random number generated by the second random number generation part on a random number generated by the first random number generation part when generating a first random number after start of supplying electric power.
摘要翻译： 一种随机数生成装置，包括：第一随机数生成部，其基于先前生成的随机数生成新的随机数，并输出由所述第一随机数生成部生成的随机数，所述随机数生成装置包括： 第二随机数生成部，其生成与由所述第一随机数生成部生成的随机数不同的随机数; 以及操作部，其在开始供给电力之后生成第一随机数时，使用由所述第二随机数生成部生成的随机数，对由所述第一随机数生成部生成的随机数，输出通过规定的操作获得的随机数 。
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5.发明申请Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses 有权用于产生确定性，非重复，伪随机地址的方法和装置公开(公告)号：US20050149591A1
公开(公告)日：2005-07-07
申请号：US11057596
申请日：2005-02-15
申请人： Kevin Duncan
发明人： Kevin Duncan
CPC分类号： G11C29/56004 , G06F7/58 , G06F7/586 , G11C29/10 , G11C29/56
摘要： A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
摘要翻译： 公开了一种用于快速生成一系列非重复，确定性，伪随机地址的系统和方法。 一个确定性的伪随机数发生器在硬件中实现。 一旦生成伪随机序列中的数字，模式消除器就会改变数字，以消除低阶位中存在的任何模式。 该数字然后可以与偏移量和基数组合以形成用于测试存储器件的存储器地址。 生成的存储器地址直接输出到被测试的存储器件。
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6.发明授权公开(公告)号：US06865660B2
公开(公告)日：2005-03-08
申请号：US10183370
申请日：2002-06-28
申请人： Kevin Duncan
发明人： Kevin Duncan
CPC分类号： G11C29/56004 , G06F7/58 , G06F7/586 , G11C29/10 , G11C29/56
摘要： A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
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公开(公告)号：US20040162863A1
公开(公告)日：2004-08-19
申请号：US10366383
申请日：2003-02-14
IPC分类号： G06F001/02
CPC分类号： G06F7/586
摘要： In the method of generating a pseudo random number, pseudo random numbers equal to pseudo random numbers generated from a pseudo random number generation function indexed by orders of two are stored. Then, a pseudo random number is generated based on the stored pseudo random numbers.
摘要翻译： 在生成伪随机数的方法中，存储等于由二阶索引的伪随机数生成函数生成的伪随机数的伪随机数。 然后，基于存储的伪随机数生成伪随机数。
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8.发明申请Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses 失效用于产生确定性，非重复，伪随机地址的方法和装置公开(公告)号：US20040006680A1
公开(公告)日：2004-01-08
申请号：US10183370
申请日：2002-06-28
发明人： Kevin Duncan
IPC分类号： G06F012/00
CPC分类号： G11C29/56004 , G06F7/58 , G06F7/586 , G11C29/10 , G11C29/56
摘要： A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
摘要翻译： 公开了一种用于快速生成一系列非重复，确定性，伪随机地址的系统和方法。 一个确定性的伪随机数发生器在硬件中实现。 一旦生成伪随机序列中的数字，模式消除器就会改变数字，以消除低阶位中存在的任何模式。 该数字然后可以与偏移量和基数组合以形成用于测试存储器件的存储器地址。 生成的存储器地址直接输出到被测试的存储器件。
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9.发明授权Pseudo-random number generator capable of efficiently exploiting processors having instruction-level parallelism and the use thereof for encryption 失效能够高效利用具有指令级并行性的处理器的伪随机数发生器及其用于加密的用途
公开(公告)号：US5983252A
公开(公告)日：1999-11-09
申请号：US7944
申请日：1998-01-16
申请人： Craig S. K. Clapp
发明人： Craig S. K. Clapp
CPC分类号： G06F7/582 , G06F7/586 , H04L9/0668 , H04L2209/125
摘要： In a finite state machine having a plurality of registers, a stream of pseudo-random numbers is generated by a method having characteristic non-zero integral value N. Repeatedly, over a series of time steps, a set of N combined values is calculated by applying N non-linear combining functions to N input sets of values and registering each combined value in one of N registers. At any time step after N time steps each input set consists of combined values, except that one input set may include as one value the result of combining a combined value with a value from an input stream, and at least two input sets comprise only registered values from distinct registers.
摘要翻译： 在具有多个寄存器的有限状态机中，通过具有特征非零积分值N的方法产生伪随机数流。重复地，通过一系列时间步长，通过以下方式计算一组N个合并值： 将N个非线性组合函数应用于N个输入值集合，并将每个组合值注册在N个寄存器之一中。 在N个时间步长之后的任何时间步骤，每个输入集合由组合值组成，除了一个输入集合可以包括将组合值与来自输入流的值组合的一个值，并且至少两个输入集合仅包括注册 来自不同寄存器的值。
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公开(公告)号：US3838259A
公开(公告)日：1974-09-24
申请号：US34822173
申请日：1973-04-05
发明人： KORTENHAUS D
CPC分类号： G06F7/586
摘要： A circuit for generating pseudo random numbers includes an adder stage having a multiplier connected for serial bit multiple addition. The adder stage is controlled by a sequence switch. The adder stage includes a first register connected to receive a preceding random number, a second register having a constant number, means connected for the serial addition of the outputs of the first and second registers, and a sum register connected to receive the results of the multiple addition. The output of the sum register is connected to the input of the first register under control of the sequence switch. An additional register may be provided, in addition to serial subtractor means for combining the outputs of the sum register and the additional register.
摘要翻译： 用于产生伪随机数的电路包括具有连接用于串行比特多加的乘法器的加法器级。 加法器级由序列开关控制。 加法器级包括连接以接收前一个随机数的第一寄存器，具有常数的第二寄存器，连接用于串行附加第一和第二寄存器的输出的装置，以及用于接收第一寄存器的结果的和寄存器 多加。 和寄存器的输出在顺序开关的控制下连接到第一个寄存器的输入。 除了用于组合和和寄存器的输出和附加寄存器的串行减法器装置之外，还可以提供附加寄存器。
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