公开(公告)号：US09081608B2

公开(公告)日：2015-07-14

申请号：US13475979

申请日：2012-05-19

申请人： Eric B. Olsen

发明人： Eric B. Olsen

IPC分类号： G06F7/72 ,  G06F7/483

CPC分类号： G06F7/483 ,  G06F7/729 ,  G06F9/30025

摘要： Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

摘要翻译： 基于残余数量系统的ALU，处理器和其他硬件的方法和系统提供全面的算术运算，同时利用某些操作中残留数的优点。 在一个或多个实施例中，RNS ALU或处理器包括被配置为执行模数运算功能的多个数字片。 数字切片的操作可由控制器控制。 残留数字可以转换为固定或混合基数系统，以供内部使用和用于各种计算系统。

公开(公告)号：US20130311532A1

公开(公告)日：2013-11-21

申请号：US13475979

申请日：2012-05-19

申请人： Eric B. Olsen

发明人： Eric B. Olsen

IPC分类号： G06F7/57

CPC分类号： G06F7/483 ,  G06F7/729 ,  G06F9/30025

摘要： Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

摘要翻译： 基于残余数量系统的ALU，处理器和其他硬件的方法和系统提供全面的算术运算，同时利用某些操作中残留数的优点。 在一个或多个实施例中，RNS ALU或处理器包括被配置为执行模数运算功能的多个数字片。 数字切片的操作可由控制器控制。 残留数字可以转换为固定或混合基数系统，以供内部使用和用于各种计算系统。

公开(公告)号：US20120284319A1

公开(公告)日：2012-11-08

申请号：US13471197

申请日：2012-05-14

申请人： Jonathon D. Mellott

发明人： Jonathon D. Mellott

IPC分类号： G06F7/38

CPC分类号： H03M7/18 ,  G06F7/729

摘要： The subject invention pertains to a method and apparatus for performing computations using residue arithmetic. The subject method and apparatus can utilize logic gates for performing calculations such as multiplication by a constant, computing a number theoretic logarithm of a residue for a given base αi and modulus pi, and computing the product of two residues, modulo pi. The use of logic gates can offer advantages when compared with the use of ROMs for table look-up functions in integrated RNS digital signal processor implementations.

摘要翻译： 本发明涉及一种使用残差运算进行计算的方法和装置。 本发明的方法和装置可以利用逻辑门进行计算，例如乘以常数，计算给定基准αi和模数pi的残差的数理论对数，以及计算两个残差（pi）的乘积。 与使用集成RNS数字信号处理器实现中的表查找功能的ROM相比，使用逻辑门可以提供优势。

公开(公告)号：US20100030832A1

公开(公告)日：2010-02-04

申请号：US12407271

申请日：2009-03-19

申请人： Jonathon D. Mellott

发明人： Jonathon D. Mellott

IPC分类号： G06F7/38

CPC分类号： H03M7/18 ,  G06F7/729

摘要： The subject invention pertains to a method and apparatus for performing computations using residue arithmetic. The subject method and apparatus can utilize logic gates for performing calculations such as multiplication by a constant, computing a number theoretic logarithm of a residue for a given base αi and modulus pi and computing the product of two residues, modulo Pi- The use of logic gates can offer advantages when compared with the use of ROMs for table look-up functions in integrated RNS digital signal processor implementations.

摘要翻译： 本发明涉及一种使用残差运算进行计算的方法和装置。 主题方法和装置可以利用逻辑门执行计算，例如乘以常数，计算给定基本α和模数pi的残差的数理论对数，并计算两个残差的乘积，模Pi-使用逻辑 与使用集成RNS数字信号处理器实现中的表查找功能的ROM相比，门可以提供优势。

公开(公告)号：US07254600B2

公开(公告)日：2007-08-07

申请号：US10665801

申请日：2003-09-18

申请人： Pierre-Yvan Liardet

发明人： Pierre-Yvan Liardet

IPC分类号： G06F7/72

CPC分类号： G06F7/729 ,  G06F2207/7223

摘要： A method and a circuit for masking digital data handled by an algorithm and factorized by a residue number system based on a finite base of numbers or polynomials prime to one another, comprising making the factorization base variable.

摘要翻译： 一种用于屏蔽由算法处理的数字数据的方法和电路，其包括使所述因式分解基变量，所述方法和电路用于屏蔽由算法处理的数字数据，并且由基于有限基数的多项式由残差数系统分解。

公开(公告)号：US20050182809A1

公开(公告)日：2005-08-18

申请号：US11106109

申请日：2005-04-14

申请人： Steven Robinson ,  William Chren

发明人： Steven Robinson ,  William Chren

IPC分类号： G06F5/01 ,  G06F7/38 ,  G06F7/72

CPC分类号： G06F7/729 ,  G06F5/01

摘要： A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.

摘要翻译： 模R加法器和用于RNS的模m，i，j比例缩放单元。 该加法器包括一个模数转换器，以及耦合到桶形移位器以存储桶形移位器的输出的动态存储单元。 在优选实施例中，动态存储单元包括用于桶形移位器的每个输出线的一个动态锁存器，每个动态锁存器包括与逆变器级联的时钟反相器。 一个模数m i，j个缩放单元包括执行残差转换和算术运算两者的修改后的模数移位器。 在不使用组合逻辑的情况下执行残余转换。 在一个优选实施例中，经修改的桶形移位器通过复制正常列的所有模m i / / SUB来执行残余转换 >输入线，它们是等同的模m m。 另一个模数转换单元包括基于桶形移位器的运算电路，以及耦合到运算电路以存储运算电路的输出的动态存储单元。

公开(公告)号：US06662201B1

公开(公告)日：2003-12-09

申请号：US09699481

申请日：2000-10-31

申请人： Shinichi Kawamura

发明人： Shinichi Kawamura

IPC分类号： G06F772

CPC分类号： G06F7/729 ,  G06F7/723

摘要： In a modular arithmetic apparatus including a plurality of product-sum circuits having a modular arithmetic function and parallelly arranged, and a correction term calculation unit for calculating a correction term to be used for modular arithmetic operation in the product-sum circuits, the correction term calculation unit sequentially calculates the correction term in units of bits, and each of the product-sum circuits sequentially reflects the correction term calculated by the correction term calculation unit and performs base conversion or base extension.

摘要翻译： 在包括具有模数运算功能并并列布置的多个积和电路的模运算装置中，以及校正项计算单元，用于计算乘积和电路中用于模运算的校正项，校正项 计算单元以位为单位顺序地计算校正项，并且乘积和电路中的每一个顺序地反映由校正项计算单元计算的校正项，并执行基本转换或基本扩展。

公开(公告)号：US5117383A

公开(公告)日：1992-05-26

申请号：US556430

申请日：1990-07-24

申请人： Tadao Fujita ,  Yoshiaki Inaba ,  Jun Takayama

发明人： Tadao Fujita ,  Yoshiaki Inaba ,  Jun Takayama

IPC分类号： G06F7/72 ,  G06F11/10 ,  G06F11/14 ,  H03H17/00 ,  H03H17/02 ,  H03M7/18

CPC分类号： G06F11/1497 ,  G06F11/104 ,  G06F7/729 ,  H03M7/18

摘要： A digital signal processing circuit of a so-called RNS system in which a residue number system ("RNS") encoder for converting input data into RNS code data is provided with a converter for connecting the input data into a multiple of one or more of the moduli of the RNS code. The converter is operated in the case of occurrence of trouble in the processing system of the modulus to locate the site of the trouble on the basis of the output of the digital signal processing circuit.

公开(公告)号：US4281391A

公开(公告)日：1981-07-28

申请号：US3745

申请日：1979-01-15

申请人： Alan Huang

发明人： Alan Huang

IPC分类号： G06F7/72 ,  H03M7/18 ,  H03K13/24

CPC分类号： G06F7/729 ,  H03M7/18

摘要： Input data is converted into its modular equivalents. These equivalents are used to perform the desired computation in a modular manner. Each computation is done for several moduli. The various modular results are woven into a mixed radix version of the answer. This version of the answer is then converted into a normal radix equivalent.The processor is constructed from a network of nodes. These nodes either store constants, perform modular arithmetic, or perform three operand binary arithmetic. The nodes are organized in networks to perform encoding, modular computations, residue to mixed radix decoding, and mixed to normal radix conversion. These operations are performed in a parallel manner. The function of the nodes can be performed by table lookup. The table lookups can be implemented with memories. The interconnection of the nodes is structured to facilitate the construction and modification of such processors. Processors can be implemented to perform many types of operations. Processors which perform summation, inner products, determinate evaluation, and summation of the squares of differences are discussed.

摘要翻译： 输入数据被转换为其模块化等价物。 这些等效物用于以模块化方式执行所需的计算。 每个计算都是针对多个模数进行的。 各种模块化结果被编织成混合基数版本的答案。 答案的这个版本然后被转换成正常的基数当量。 处理器由节点网络构成。 这些节点存储常量，执行模数运算，或执行三个操作数二进制运算。 节点被组织在网络中以执行编码，模块化计算，残差混合基数解码，并混合到正常的基数转换。 这些操作以并行方式执行。 节点的功能可以通过表查找来执行。 表查找可以用记忆来实现。 结构的互连被构造成便于这种处理器的构造和修改。 可以实现处理器来执行许多类型的操作。 讨论了执行求和，内积，确定性评估和差异平方和的处理器。

公开(公告)号：US20190235841A1

公开(公告)日：2019-08-01

申请号：US16380267

申请日：2019-04-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Steven R. Carlough ,  Klaus M. Kroener ,  Silvia Melitta Mueller ,  Andreas Wagner

IPC分类号： G06F7/72 ,  G06F7/48

CPC分类号： G06F7/729 ,  G06F7/48

摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.