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公开(公告)号：US11662257B2
公开(公告)日：2023-05-30
申请号：US16919966
申请日：2020-07-02
Applicant: Nokia Technologies Oy
Inventor： Marijan Herceg , Tomislav Matic
CPC classification number: G01K7/16 , G01K1/024 , G01K1/08 , G01K3/005 , G11C11/00 , G11C11/21 , G11C13/0002 , G11C13/0021 , G11C13/0097
Abstract: An apparatus comprising: a memristor; means for wirelessly receiving, from another apparatus, a time-varying signal; means for enabling, responsive to the received time-varying signal, provision of one or more pulses to the memristor to change an electrical characteristic of the memristor; means for wirelessly signalling to the other apparatus when the electrical characteristic of the memristor reaches a threshold value; and means for re-setting the electrical characteristic of the memristor.
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2.发明申请
公开(公告)号：US20190221265A1
公开(公告)日：2019-07-18
申请号：US16363850
申请日：2019-03-25
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Satoshi INOUE , Daisuke ARIZONO
CPC classification number: G11C16/06 , G11C7/04 , G11C7/10 , G11C7/1057 , G11C7/1084 , G11C11/00 , G11C16/0483 , G11C16/26 , G11C2207/2254
Abstract: A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.
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公开(公告)号：US20190206939A1
公开(公告)日：2019-07-04
申请号：US15859259
申请日：2017-12-29
Applicant: Spin Memory, Inc.
Inventor： Kadriye Deniz Bozdag , Marcin Gajek , Mourad El Baraji , Eric Michael Ryan
CPC classification number: G11C11/15 , G11C11/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.
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公开(公告)号：US20190156887A1
公开(公告)日：2019-05-23
申请号：US15821240
申请日：2017-11-22
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Jeremy M. Hirst
IPC: G11C13/00
CPC classification number: G11C13/0061 , G11C11/00 , G11C11/22 , G11C11/221 , G11C11/223 , G11C11/5657 , G11C13/004 , G11C2013/0054
Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.
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公开(公告)号：US20180277216A1
公开(公告)日：2018-09-27
申请号：US15699847
申请日：2017-09-08
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Satoshi INOUE , Daisuke ARIZONO
CPC classification number: G11C16/06 , G11C7/04 , G11C7/10 , G11C7/1057 , G11C7/1084 , G11C11/00 , G11C2207/2254
Abstract: According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.
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6.发明授权
公开(公告)号：US09990976B1
公开(公告)日：2018-06-05
申请号：US15409757
申请日：2017-01-19
Applicant: Everspin Technologies, Inc.
Inventor： Jon Slaughter
CPC classification number: G11C11/1675 , G11C11/00 , G11C11/161 , G11C11/1673 , G11C11/18 , G11C11/5607 , G11C13/0035 , G11C13/004
Abstract: A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells.
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公开(公告)号：US20180137915A1
公开(公告)日：2018-05-17
申请号：US15869751
申请日：2018-01-12
Applicant: Western Digital Technologies, Inc.
Inventor： James Edwin O'TOOLE , Ward PARKINSON , Daniel Robert SHEPARD , Thomas Michael TRENT
CPC classification number: G11C5/14 , G11C7/00 , G11C11/00 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/76 , H01L27/2427 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146
Abstract: The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.
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公开(公告)号：US20180130525A1
公开(公告)日：2018-05-10
申请号：US15865036
申请日：2018-01-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jhon-Jhy LIAW
IPC: G11C11/419 , G11C11/00 , G11C11/412 , G11C7/12
CPC classification number: G11C11/419 , G11C7/12 , G11C11/00 , G11C11/412 , G11C11/4125
Abstract: A semiconductor memory is disclosed that includes a first data line, a first coupling line, and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively couple the second coupling line with the first data line. The first data line and the first coupling line are formed in a first conductive layer, and the second coupling line is formed in a second conductive layer that is different from the first conductive layer.
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公开(公告)号：US09965214B2
公开(公告)日：2018-05-08
申请号：US15808367
申请日：2017-11-09
Applicant: SK hynix Inc.
Inventor： Jae-Han Park , Hyun-Woo Kwack
CPC classification number: G06F3/0647 , G06F3/0604 , G06F3/0683 , G11C5/04 , G11C7/10 , G11C11/00
Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
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公开(公告)号：US09924593B2
公开(公告)日：2018-03-20
申请号：US15254353
申请日：2016-09-01
Applicant: Kabushiki Kaisha Toshiba
Inventor： Tadashi Sakai , Yuichi Yamazaki , Hisao Miyazaki , Masayuki Katagiri , Taishi Ishikura , Akihiro Kajita
CPC classification number: H05K1/09 , G11C11/00 , H01L21/768 , H01L21/7682 , H01L21/76831 , H01L21/76879 , H01L21/76885 , H01L23/5283 , H01L23/53276 , H05K1/0306 , H05K1/115 , H05K3/146 , H05K3/4076 , H05K2201/0323
Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.
