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公开(公告)号：US20190180840A1
公开(公告)日：2019-06-13
申请号：US15988970
申请日：2018-05-24
Inventor： Sungho KANG , Dong Hyun HAN
IPC: G11C29/00
CPC classification number: G11C29/72 , G11C29/76 , G11C29/814 , G11C29/846 , G11C2029/5602
Abstract: Disclosed are a stacked memory device and a method of repairing the same, in which spare cells for a post-bond test and repair process are disposed in a base die and the spare cells are used in each memory layer as many as the number desired, a repair result after the test is permanently stored, and the spare cell of the base die and the memory layer are simultaneously approached and meaningful data is selected, so that it is not necessary to newly perform a test even though power of a memory is blocked, it is possible to solve time wasted during an approach to a memory layer after a spare memory performs determination, and it is possible to secure a high repair rate.
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公开(公告)号：US20180308562A1
公开(公告)日：2018-10-25
申请号：US15593326
申请日：2017-05-12
Applicant: NXP USA, INC.
Inventor： XUEWEN HE , Xiaoxeng Geng , Lei Zhang
CPC classification number: G11C29/44 , G06F11/2094 , G06F2201/805 , G06F2201/82 , G11C29/4401 , G11C29/76 , G11C29/789 , G11C29/808 , G11C29/846 , G11C2029/0403 , G11C2029/1208 , G11C2029/4402
Abstract: An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.
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公开(公告)号：US20180308539A1
公开(公告)日：2018-10-25
申请号：US16020863
申请日：2018-06-27
Applicant: Micron Technology, Inc.
Inventor： Yutaka Ito , Yuan He
IPC: G11C11/406 , G11C29/00 , G11C11/408
CPC classification number: G11C11/40611 , G11C11/406 , G11C11/4087 , G11C29/72 , G11C29/783 , G11C29/846
Abstract: A semiconductor device according to an aspect of die present invention has: a plurality of memory cells MC: a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to, the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against for example, the Row Hammer problem, etc. can be taken.
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公开(公告)号：US20180005709A1
公开(公告)日：2018-01-04
申请号：US15589308
申请日：2017-05-08
Applicant: Intel Corporation
Inventor： Joon-Sung YANG , Darshan KOBLA , Liwei JU , David ZIMMERMAN
CPC classification number: G11C29/70 , G11C29/025 , G11C29/04 , G11C29/4401 , G11C29/702 , G11C29/785 , G11C29/846 , G11C2213/71 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2225/06544 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
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公开(公告)号：US09734921B2
公开(公告)日：2017-08-15
申请号：US14407318
申请日：2013-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Suresh Rajan , Ian Shaeffer
CPC classification number: G11C29/4401 , G06F11/1016 , G06F11/1072 , G11C29/808 , G11C29/846
Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.
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公开(公告)号：US20170212816A1
公开(公告)日：2017-07-27
申请号：US15146532
申请日：2016-05-04
Applicant: SK hynix Inc.
Inventor： Sok Kyu LEE
CPC classification number: G06F11/2017 , G06F11/1044 , G06F11/1679 , G11C16/0483 , G11C29/702 , G11C29/846
Abstract: A data storage device includes a semiconductor memory device including a memory cell array which includes a main cell area and a spare cell area; and a controller coupled with the semiconductor memory device through a plurality of main data lines and at least one spare data line, and configured to transmit main data to be stored in the main cell area, through the plurality of main data lines, and transmit spare data for managing the main data to be stored in the spare cell area, through the spare data line.
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公开(公告)号：US09711243B1
公开(公告)日：2017-07-18
申请号：US15188876
申请日：2016-06-21
Applicant: ARM Limited
Inventor： Vivek Nautiyal , Fakhruddin Ali Bohra , Satinderjit Singh , Jitendra Dasani , Shri Sagar Dwivedi
IPC: G11C11/00 , G11C29/00 , G11C11/412 , G11C11/417
CPC classification number: G11C29/76 , G11C11/417 , G11C29/12 , G11C29/842 , G11C29/846
Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first memory cell array disposed in a first area of the integrated circuit. The first memory cell array includes first memory cells. The integrated circuit may include a second memory cell array disposed in a second area of the integrated circuit that is different than the first area. The second memory cell array includes redundant memory cells that are separate from the first memory cells.
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公开(公告)号：US09343438B1
公开(公告)日：2016-05-17
申请号：US14711388
申请日：2015-05-13
Applicant: SK hynix Inc.
Inventor： Hyun Sung Lee
IPC: H01L25/065 , H01L27/02
CPC classification number: H01L27/0207 , G11C29/846 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
Abstract: A semiconductor apparatus may include a plurality of core chips and a base chip. The plurality of core chips may respectively include a plurality of channels, and each of the plurality of channels may include at least two pseudo channels. Each of the plurality of core chips may include a channel selection unit that selects one or more of the pseudo channels based on a channel mode signal, a pseudo channel signal, a stack information signal, and a slice information signal.
Abstract translation: 半导体装置可以包括多个芯片芯片和基底芯片。 多个核心芯片可以分别包括多个信道，并且多个信道中的每一个可以包括至少两个伪信道。 多个核心芯片中的每一个可以包括基于信道模式信号，伪信道信号，堆叠信息信号和片信息信号来选择一个或多个伪信道的信道选择单元。
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公开(公告)号：US09218894B2
公开(公告)日：2015-12-22
申请号：US13963831
申请日：2013-08-09
Applicant: BROADCOM CORPORATION
Inventor： Ilan Strulovici , Yizhak Feldman
CPC classification number: G11C29/4401 , G11C29/785 , G11C29/808 , G11C29/846
Abstract: A device for repairing a memory device using a test-bypass register associated with the memory device may include a comparator configured to compare a current address of the memory device with a faulty address and to generate a match signal when the current address matches the faulty address. A logic block may be coupled to the comparator and configured to generate one or more output signals in response to the match signal. The faulty address may be associated with a non-operational cell of the memory device. The one or more output signals may be coupled to one or more memory-bypass inputs of the test-bypass register. The one or more output signals may be configured to enable use of the test-bypass register instead of the non-operational cell of the memory device.
Abstract translation: 使用与存储器件相关联的测试旁路寄存器修复存储器件的设备可以包括比较器，其被配置为将存储器件的当前地址与错误地址进行比较，并且当当前地址与故障地址匹配时产生匹配信号 。 逻辑块可以耦合到比较器并且被配置为响应于匹配信号而产生一个或多个输出信号。 故障地址可以与存储器件的非操作单元相关联。 一个或多个输出信号可以耦合到测试旁路寄存器的一个或多个存储器旁路输入。 一个或多个输出信号可以被配置为能够使用测试旁路寄存器而不是存储器件的非操作单元。
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公开(公告)号：US20150254010A1
公开(公告)日：2015-09-10
申请号：US14482697
申请日：2014-09-10
Applicant: Kabushiki Kaisha Toshiba
Inventor： Hiromitsu KOMAI
IPC: G06F3/06
CPC classification number: G11C29/82 , G06F12/0607 , G11C16/0483 , G11C29/846
Abstract: A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.
Abstract translation: 半导体存储装置具有单元阵列，与单元阵列逻辑地分离的冗余阵列，具有通过一次存取从单元阵列读取或写入的数据的存储区域的高速缓存存储器，存储列阵列的列地址 单元阵列中的有缺陷的列，缺陷列确定模块，用于确定要访问的列地址是否与存储在缺陷列存储器中的列地址匹配;以及时钟发生器，用于生成用于访问每个分割区域的时钟 并且当缺陷列确定模块确定存在匹配时，而不是在访问分割页缓冲区的时钟的生成定时处访问划分页缓冲区的时钟。
