公开(公告)号：US09508689B2

公开(公告)日：2016-11-29

申请号：US14871185

申请日：2015-09-30

申请人： Invensas Corporation

发明人： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

公开(公告)号：US08963326B2

公开(公告)日：2015-02-24

申请号：US13312730

申请日：2011-12-06

申请人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

发明人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

摘要翻译： 半导体器件具有在半导体晶片的表面上形成有第一导电层的半导体晶片。 在半导体晶片和第一导电层的表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 在半导体晶片的凸块形成区域中的第二绝缘层中形成多个开口以暴露第二导电层并减少电迁移的不利影响。 开口由第二绝缘层的一部分分开。 UBM层形成在电连接到第二导电层的凸块形成区域中的第二绝缘层的开口上方。 在UBM层上形成凸点。

公开(公告)号：US20120007254A1

公开(公告)日：2012-01-12

申请号：US13092895

申请日：2011-04-22

申请人： Chih-kuang YANG

发明人： Chih-kuang YANG

IPC分类号： H01L23/48 ,  H05K1/11 ,  H05K1/00

CPC分类号： H05K3/4679 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0362 ,  H01L2224/03632 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K1/0393 ,  H05K3/048 ,  H05K2201/096 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall.

摘要翻译： 公开了一种多层通孔结构，包括金属层，形成在第一介电层的第一开口上的第一通孔金属层和形成在第二介电层的第二开口上的第二通孔金属层。 第一和第二通孔金属层分别包括第一和第二底部，第一和第二顶部，第一和第二倾斜壁。 第一和第二倾斜壁分别包括第一和第二顶部边缘，第一和第二底部边缘。 第二顶边具有最靠近第一底部的几何中心的点。 该点的垂直投影落在第一倾斜壁上。 或者，最靠近几何中心的第二底部边缘的点具有垂直投影。 垂直投影垂直于金属层，并落在第一倾斜壁上。

公开(公告)号：US20180076160A1

公开(公告)日：2018-03-15

申请号：US15813311

申请日：2017-11-15

申请人： International Business Machines Corporation

发明人： Brian M. Erwin ,  Brittany L. Hedrick ,  Nicholas A. Polomoff ,  TaeHo Kim ,  Matthew E. Souter

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11632 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13686 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/053

摘要： A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

公开(公告)号：US20160027761A1

公开(公告)日：2016-01-28

申请号：US14871185

申请日：2015-09-30

申请人： Invensas Corporation

发明人： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC分类号： H01L25/065 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

摘要翻译： 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：US20120119385A1

公开(公告)日：2012-05-17

申请号：US13109996

申请日：2011-05-17

申请人： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  DeAnn Elleen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. del Rosario ,  John R. Bray

发明人： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  DeAnn Elleen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. del Rosario ,  John R. Bray

IPC分类号： H01L23/52 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

摘要翻译： 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：US20180337116A1

公开(公告)日：2018-11-22

申请号：US15598304

申请日：2017-05-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po-Chun LIN ,  Chin-Lung CHU

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/482 ,  H01L24/02 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/02381 ,  H01L2224/0311 ,  H01L2224/034 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0605 ,  H01L2224/06102 ,  H01L2224/06179 ,  H01L2224/06183 ,  H01L2224/06515 ,  H01L2224/113 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14179 ,  H01L2224/14183 ,  H01L2224/14515 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16137 ,  H01L2224/16141 ,  H01L2224/17051 ,  H01L2224/17152 ,  H01L2224/17179 ,  H01L2224/17183 ,  H01L2224/1751 ,  H01L2225/065

摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

公开(公告)号：US09754823B2

公开(公告)日：2017-09-05

申请号：US14288840

申请日：2014-05-28

申请人： International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

发明人： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC分类号： H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

摘要： A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

公开(公告)号：US20150348831A1

公开(公告)日：2015-12-03

申请号：US14288840

申请日：2014-05-28

申请人： International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

发明人： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC分类号： H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

摘要： A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

摘要翻译： 在衬底上选择性地定位阻挡层的方法包括在衬底的表面上形成阻挡层。 阻挡层由金属元素和非金属元素组成。 阻挡层也可以由金属元素和非金属元素形成。 该方法还包括在阻挡层上形成导电膜层，并在导电膜层中形成金属部分。 该方法还包括从电介质层选择性地烧蚀阻挡层的部分，以选择性地将阻挡层定位在衬底上。

公开(公告)号：US20130140691A1

公开(公告)日：2013-06-06

申请号：US13312730

申请日：2011-12-06

申请人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

发明人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC分类号： H01L23/498 ,  H01L21/28

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.