公开(公告)号：US09269617B2

公开(公告)日：2016-02-23

申请号：US14514570

申请日：2014-10-15

Applicant: NXP B.V.

Inventor： Yuan Li ,  Som Nath ,  Maarten van Dort

IPC: H01L21/326 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/76805 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01022 ,  H01L2924/01007 ,  H01L2924/01073 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/48

Abstract: A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.

Abstract translation: 电路设备配置有鲁棒的电路连接器。 结合各种示例实施例，集成电路器件包括在接合焊盘触点下方的一个或多个通孔网络层，将接合焊盘触点与一个或多个下面的金属层相连接。 每个通孔网络层包括多个通孔，其平行于接合焊盘触点并沿不同的方向延伸，以在结构上支撑接合焊盘触点。

公开(公告)号：US20130256893A1

公开(公告)日：2013-10-03

申请号：US13435702

申请日：2012-03-30

Applicant: Tsung-Han TSAI ,  Jung-Chi JENG ,  Yueh-Ching CHANG ,  Volume CHIEN ,  Huang-Ta HUANG ,  Chi-Cherng JENG

Inventor： Tsung-Han TSAI ,  Jung-Chi JENG ,  Yueh-Ching CHANG ,  Volume CHIEN ,  Huang-Ta HUANG ,  Chi-Cherng JENG

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05085 ,  H01L2224/05086 ,  H01L2224/05087 ,  H01L2224/05088 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.

Abstract translation: 焊盘结构包括基板和形成在第一电介质层中并设置在基板上的第一导电岛。 具有多个通孔的第一通孔阵列形成在第二电介质层中并设置在第一导电岛上。 第二导电岛形成在第三电介质层中并且设置在第一通孔阵列上。 焊盘设置在第二导电岛上。 第一导电岛，第一通孔阵列和第二导电岛电连接到接合焊盘。 除了第一导电岛之外，第一通孔阵列连接到第一电介质层中没有其它导电岛。 除了第二导电岛之外，第三电介质层中没有其它导电岛连接到第一通孔阵列。

公开(公告)号：US20180096958A1

公开(公告)日：2018-04-05

申请号：US15663531

申请日：2017-07-28

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

Inventor： YUNLONG KONG

IPC: H01L23/00 ,  H01L27/146 ,  H04N5/369

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/0212 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/48227 ,  H01L2224/73265 ,  H04N5/369 ,  H01L2924/00014

Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.

公开(公告)号：US09711468B2

公开(公告)日：2017-07-18

申请号：US14683204

申请日：2015-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Han Tsai ,  Jung-Chi Jeng ,  Yueh-Ching Chang ,  Volume Chien ,  Huang-Ta Huang ,  Chi-Cherng Jeng

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05085 ,  H01L2224/05086 ,  H01L2224/05087 ,  H01L2224/05088 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.

公开(公告)号：US09666546B1

公开(公告)日：2017-05-30

申请号：US15141571

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L23/31 ,  H01L21/768

CPC classification number: H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US09475693B2

公开(公告)日：2016-10-25

申请号：US14732998

申请日：2015-06-08

Applicant: Robert Bosch GmbH

Inventor： Daniel Christoph Meisel ,  Christoph Schelling ,  Torsten Kramer ,  Jens Frey

IPC: B81B7/00 ,  H01L23/48 ,  H01L25/065 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05097 ,  H01L2224/05098 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/01029 ,  H01L2924/014

Abstract: Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Abstract translation: 提供了用于稳定ASIC元件的连接区域的子结构的措施。 这些措施涉及ASIC元件，包括集成了电路功能的ASIC基板，并且在ASIC基板上包括ASIC层结构，其包括用于电路功能的多个布线层，它们通过绝缘层彼此分开，并且 通过金属插头互连。 用于放置线接合或用于晶片接合的至少一个连接区域在至少一个最上面的布线层中实现。 在直接布线垂直布置的至少一个金属插塞链在从连接区域下方的ASIC层结构中实现，该连接区域从最上面的布线层向上延伸到ASIC衬底或引入其中的氧化物沟槽。

公开(公告)号：US07985671B2

公开(公告)日：2011-07-26

申请号：US12344774

申请日：2008-12-29

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05088 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该方法包括在电介质层中形成上布线层，并在上布线层上淀积一层或多层介电层。 该方法还包括在延伸到上布线层的一个或多个电介质层中形成多个离散的沟槽。 该方法还包括在多个离散的沟槽中沉积限制极限的冶金或凸块下的冶金，以形成与上部绞合层接触的离散的金属岛。 形成与多个离散金属岛电连接的焊料凸块。

公开(公告)号：US11804460B2

公开(公告)日：2023-10-31

申请号：US17676602

申请日：2022-02-21

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Jiro Yota ,  Dogan Gunes

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/10

CPC classification number: H01L24/11 ,  H01L23/10 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/0509 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05078 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05558 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29082 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2924/12 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/35121 ,  H01L2224/05558 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05005 ,  H01L2924/00012 ,  H01L2224/05018 ,  H01L2924/00012 ,  H01L2224/05098 ,  H01L2924/06 ,  H01L2224/02125 ,  H01L2924/00012 ,  H01L2224/0215 ,  H01L2924/06 ,  H01L2224/05012 ,  H01L2924/00012 ,  H01L2224/05093 ,  H01L2924/00012 ,  H01L2224/0509 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/83

Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

公开(公告)号：US20150353343A1

公开(公告)日：2015-12-10

申请号：US14732998

申请日：2015-06-08

Applicant: Robert Bosch GmbH

Inventor： Daniel Christoph MEISEL ,  Christoph SCHELLING ,  Torsten KRAMER ,  Jens FREY

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05097 ,  H01L2224/05098 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/01029 ,  H01L2924/014

Abstract: Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Abstract translation: 提供了用于稳定ASIC元件的连接区域的子结构的措施。 这些措施涉及ASIC元件，包括集成了电路功能的ASIC基板，并且在ASIC基板上包括ASIC层结构，其包括用于电路功能的多个布线层，它们通过绝缘层彼此分开，并且 通过金属插头互连。 用于放置线接合或用于晶片接合的至少一个连接区域在至少一个最上面的布线层中实现。 在直接布线垂直布置的至少一个金属插塞链在从连接区域下方的ASIC层结构中实现，该连接区域从最上面的布线层向上延伸到ASIC衬底或引入其中的氧化物沟槽。

公开(公告)号：US08896124B2

公开(公告)日：2014-11-25

申请号：US13079579

申请日：2011-04-04

Applicant: Yuan Li ,  Som Nath ,  Maarten Jeroen Van Dort

Inventor： Yuan Li ,  Som Nath ,  Maarten Jeroen Van Dort

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/76805 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01022 ,  H01L2924/01007 ,  H01L2924/01073 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/48

Abstract: A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.

Abstract translation: 电路设备配置有鲁棒的电路连接器。 结合各种示例实施例，集成电路器件包括在接合焊盘触点下方的一个或多个通孔网络层，将接合焊盘触点与一个或多个下面的金属层相连接。 每个通孔网络层包括多个通孔，其平行于接合焊盘触点并沿不同的方向延伸，以在结构上支撑接合焊盘触点。