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公开(公告)号:US09087833B2
公开(公告)日:2015-07-21
申请号:US14093126
申请日:2013-11-29
发明人: Baik-woo Lee , Seong-woon Booh
IPC分类号: H01L29/45 , H01L29/78 , H01L29/739 , H01L23/498 , H01L23/373 , H01L23/00 , H01L25/07 , H01L25/18 , H01L29/20
CPC分类号: H01L23/49844 , H01L23/3735 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/072 , H01L25/18 , H01L29/2003 , H01L29/7393 , H01L2224/03436 , H01L2224/0345 , H01L2224/03452 , H01L2224/04026 , H01L2224/04042 , H01L2224/05109 , H01L2224/05111 , H01L2224/05113 , H01L2224/05116 , H01L2224/05117 , H01L2224/05118 , H01L2224/05124 , H01L2224/05138 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05149 , H01L2224/05155 , H01L2224/05157 , H01L2224/05163 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/0517 , H01L2224/05173 , H01L2224/05176 , H01L2224/0518 , H01L2224/05181 , H01L2224/05183 , H01L2224/05184 , H01L2224/05559 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/0603 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29339 , H01L2224/29347 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48139 , H01L2224/48227 , H01L2224/48472 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/73265 , H01L2224/83203 , H01L2224/83801 , H01L2224/8384 , H01L2224/85205 , H01L2224/85801 , H01L2224/8584 , H01L2224/92247 , H01L2924/00011 , H01L2924/13033 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2924/2076 , H01L2924/00014 , H01L2924/01004 , H01L2924/01072 , H01L2924/01052 , H01L2924/014 , H01L2224/83205
摘要: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.
摘要翻译: 功率半导体器件可以包括:下部结构; 下部结构上的焊料层; 焊料层上的半导体结构; 半导体结构上的接触层; 接触层上的垫层; 和/或垫层和下部结构之间的线。 焊料层可以电连接到半导体结构的第一电极。
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公开(公告)号:US20180102336A1
公开(公告)日:2018-04-12
申请号:US15711016
申请日:2017-09-21
CPC分类号: H01L24/06 , H01L22/20 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05113 , H01L2224/05155 , H01L2224/05647 , H01L2224/05666 , H01L2224/0603 , H01L2224/06131 , H01L2224/06132 , H01L2224/06134 , H01L2224/06177 , H01L2224/11001 , H01L2224/1145 , H01L2224/11462 , H01L2224/116 , H01L2224/1161 , H01L2224/13026 , H01L2224/13028 , H01L2224/13078 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/13562 , H01L2224/136 , H01L2224/13639 , H01L2224/16227 , H01L2224/81815 , H01L2924/07025 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
摘要: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
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公开(公告)号:US20180012854A1
公开(公告)日:2018-01-11
申请号:US15642810
申请日:2017-07-06
发明人: Jens Oetjen , Stefan Macheiner
IPC分类号: H01L23/00 , H01L23/495
CPC分类号: H01L24/05 , H01L21/4821 , H01L23/49527 , H01L23/49582 , H01L24/03 , H01L2224/0345 , H01L2224/0346 , H01L2224/05023 , H01L2224/05113 , H01L2224/0512 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611
摘要: A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer.
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公开(公告)号:US09966322B2
公开(公告)日:2018-05-08
申请号:US15071195
申请日:2016-03-15
发明人: Hisao Teshima
IPC分类号: H01L29/417 , H01L23/00 , H01L23/528 , H01L23/31 , H01L29/78 , H01L21/78 , H01L29/861 , H01L29/732 , H01L29/74 , H01L29/739
CPC分类号: H01L23/3192 , H01L21/78 , H01L23/3185 , H01L23/528 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/94 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/732 , H01L29/7396 , H01L29/7397 , H01L29/7398 , H01L29/74 , H01L29/7809 , H01L29/7813 , H01L29/7827 , H01L29/8611 , H01L2224/02371 , H01L2224/02381 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03464 , H01L2224/0401 , H01L2224/04026 , H01L2224/05001 , H01L2224/05111 , H01L2224/05113 , H01L2224/05116 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/0518 , H01L2224/05184 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05567 , H01L2224/05613 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/0568 , H01L2224/05684 , H01L2224/0603 , H01L2224/06051 , H01L2224/10145 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/291 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/2929 , H01L2224/293 , H01L2224/29324 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32105 , H01L2224/32227 , H01L2224/81143 , H01L2224/81192 , H01L2224/81447 , H01L2224/81815 , H01L2224/81907 , H01L2224/83143 , H01L2224/83192 , H01L2224/83447 , H01L2224/83815 , H01L2224/83907 , H01L2224/94 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/35121 , H01L2924/3841 , H01L2924/00014 , H01L2924/0105 , H01L2924/01014 , H01L2924/01032 , H01L2924/01051 , H01L2924/014 , H01L2224/03 , H01L2924/01047 , H01L2924/00012 , H01L2924/00
摘要: A semiconductor device includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer has a semiconductor element. The first conductor film is formed on an upper surface of the semiconductor layer and is electrically connected to the semiconductor element. The second conductor film is formed on an outer side surface of the semiconductor layer and is electrically connected to the semiconductor element. The first protective film is formed on the first conductor film and has an opening to expose the first conductor film. A height from the upper surface of the semiconductor layer to an upper surface of the second conductor film is equal to or smaller than a height from the upper surface of the semiconductor layer to an upper surface of the first conductor film.
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公开(公告)号:US09754893B2
公开(公告)日:2017-09-05
申请号:US14861139
申请日:2015-09-22
发明人: Jingxiu Ding , Zuopeng He
IPC分类号: H01L23/544 , H01L21/68 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号: H01L23/544 , H01L21/68 , H01L24/03 , H01L24/09 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/03618 , H01L2224/05111 , H01L2224/05113 , H01L2224/05116 , H01L2224/05139 , H01L2224/08145 , H01L2224/8013 , H01L2224/80203 , H01L2224/80801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/0132 , H01L2924/0133 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109
摘要: Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy.
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公开(公告)号:US20160197023A1
公开(公告)日:2016-07-07
申请号:US15071195
申请日:2016-03-15
发明人: HISAO TESHIMA
IPC分类号: H01L23/31 , H01L23/528 , H01L29/78
CPC分类号: H01L23/3192 , H01L21/78 , H01L23/3185 , H01L23/528 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/94 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/732 , H01L29/7396 , H01L29/7397 , H01L29/7398 , H01L29/74 , H01L29/7809 , H01L29/7813 , H01L29/7827 , H01L29/8611 , H01L2224/02371 , H01L2224/02381 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03464 , H01L2224/0401 , H01L2224/04026 , H01L2224/05001 , H01L2224/05111 , H01L2224/05113 , H01L2224/05116 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/0518 , H01L2224/05184 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05567 , H01L2224/05613 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/0568 , H01L2224/05684 , H01L2224/0603 , H01L2224/06051 , H01L2224/10145 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/291 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/2929 , H01L2224/293 , H01L2224/29324 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32105 , H01L2224/32227 , H01L2224/81143 , H01L2224/81192 , H01L2224/81447 , H01L2224/81815 , H01L2224/81907 , H01L2224/83143 , H01L2224/83192 , H01L2224/83447 , H01L2224/83815 , H01L2224/83907 , H01L2224/94 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/35121 , H01L2924/3841 , H01L2924/00014 , H01L2924/0105 , H01L2924/01014 , H01L2924/01032 , H01L2924/01051 , H01L2924/014 , H01L2224/03 , H01L2924/01047 , H01L2924/00012 , H01L2924/00
摘要: A semiconductor device includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer has a semiconductor element. The first conductor film is formed on an upper surface of the semiconductor layer and is electrically. connected to the semiconductor element. The second conductor film is formed on an outer side surface of the semiconductor layer and is electrically connected to the semiconductor element. The first protective film is formed on the first conductor film and has an opening to expose the first conductor film. A height from the upper surface of the semiconductor layer to an upper surface of the second conductor film is equal to or smaller than a height from the upper surface of the semiconductor layer to an upper surface of the first conductor film.
摘要翻译: 半导体器件包括半导体层,第一导体膜,第二导体膜和第一保护膜。 半导体层具有半导体元件。 第一导体膜形成在半导体层的上表面上并且是电气的。 连接到半导体元件。 第二导体膜形成在半导体层的外侧表面上并与半导体元件电连接。 第一保护膜形成在第一导体膜上,并且具有露出第一导体膜的开口。 从半导体层的上表面到第二导体膜的上表面的高度等于或小于从半导体层的上表面到第一导体膜的上表面的高度。
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公开(公告)号:US20190184480A1
公开(公告)日:2019-06-20
申请号:US16218459
申请日:2018-12-12
IPC分类号: B23K3/06 , H01L21/683 , H01L21/68 , H01L21/67 , H01L23/00 , H01L39/24 , B23K1/00 , B23K35/02
CPC分类号: B23K3/0623 , B23K1/0016 , B23K35/0222 , B23K35/264 , B23K2101/42 , H01L21/67092 , H01L21/681 , H01L21/6836 , H01L21/6838 , H01L24/03 , H01L39/143 , H01L39/24 , H01L39/248 , H01L2221/68309 , H01L2224/03003 , H01L2224/0311 , H01L2224/05109 , H01L2224/05113 , H01L2924/01322 , H01L2924/014
摘要: A method of making precise alignment and decal bonding of a pattern of solder preforms to a surface comprising cutting and placing a length of a solder ribbon onto a semiconductor release tape forming a solder ribbon and semiconductor release tape combination, placing the solder ribbon and semiconductor release tape combination on a vacuum chuck on X-Y stage pair in a laser micromachining system, adjusting the working distance, laser-cutting an outline, peeling off the solder ribbon, allowing the desired solder shape to remain, creating indexing holes, providing a target surface on an alignment fixture with indexing pins, aligning the indexing holes, placing the semiconductor release tape with the desired solder shape on the target surface, pressing the desired solder shape onto the target surface, removing the release tape, and making a pattern of the desired solder shape with precise alignment and decal bonding on the target surface.
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公开(公告)号:US20170148754A1
公开(公告)日:2017-05-25
申请号:US15421737
申请日:2017-02-01
申请人: GlobalFoundries Inc.
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
CPC分类号: H01L21/563 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L2224/024 , H01L2224/0401 , H01L2224/05023 , H01L2224/05024 , H01L2224/05082 , H01L2224/05113 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05613 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11912 , H01L2224/13023 , H01L2224/13076 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2224/13184 , H01L2224/13186 , H01L2224/73104 , H01L2224/73204 , H01L2924/0132 , H01L2924/04941 , H01L2924/04953 , H01L2924/07025 , H01L2924/14 , H01L2924/00014 , H01L2924/01074 , H01L2924/014
摘要: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.
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公开(公告)号:US09607862B2
公开(公告)日:2017-03-28
申请号:US13610262
申请日:2012-09-11
申请人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号: H01L21/306 , H01L23/498 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号: H01L21/563 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L2224/024 , H01L2224/0401 , H01L2224/05023 , H01L2224/05024 , H01L2224/05082 , H01L2224/05113 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05613 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11912 , H01L2224/13023 , H01L2224/13076 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2224/13184 , H01L2224/13186 , H01L2224/73104 , H01L2224/73204 , H01L2924/0132 , H01L2924/04941 , H01L2924/04953 , H01L2924/07025 , H01L2924/14 , H01L2924/00014 , H01L2924/01074 , H01L2924/014
摘要: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.
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10.
公开(公告)号:US20140070401A1
公开(公告)日:2014-03-13
申请号:US13610262
申请日:2012-09-11
申请人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号: H01L21/306 , H01L23/498
CPC分类号: H01L21/563 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L2224/024 , H01L2224/0401 , H01L2224/05023 , H01L2224/05024 , H01L2224/05082 , H01L2224/05113 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05613 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11912 , H01L2224/13023 , H01L2224/13076 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2224/13184 , H01L2224/13186 , H01L2224/73104 , H01L2224/73204 , H01L2924/0132 , H01L2924/04941 , H01L2924/04953 , H01L2924/07025 , H01L2924/14 , H01L2924/00014 , H01L2924/01074 , H01L2924/014
摘要: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.
摘要翻译: 各种实施方案包括形成互连结构的方法以及通过这些方法形成的结构。 在一个实施例中,一种方法可以包括:提供具有:光敏聚酰亚胺(PSPI)层的前体互连结构; 一个控制崩溃芯片连接(C4)凸起覆盖PSPI层; 以及覆盖C4凸块并且接触C4凸块的一侧的焊料。 该方法还可以包括使与C4凸起相邻的PSPI层的一部分凹陷以在C4凸起下形成PSPI基座。 该方法还可以包括形成邻接PSPI基座和C4凸块的底部填充物,其中底部填充物和焊料形成与PSPI基座分离的界面。
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