公开(公告)号：US09331038B2

公开(公告)日：2016-05-03

申请号：US14013597

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chih-Hang Tung ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/06 ,  H01L21/56 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

Abstract translation: 导电互连结构包括接触垫; 在第一端连接到接触垫的导电体; 以及位于所述导电体的第二端上的导电层。 导电体具有垂直于接触垫表面的纵向方向。 导电体在垂直于导电体的纵向方向的截面（平面A）上具有平均粒径（a）。 导电层在平面A上具有平均粒径（b）。导电体和导电层由相同的材料组成，平均晶粒尺寸（a）大于平均晶粒尺寸（b）。

公开(公告)号：US09324557B2

公开(公告)日：2016-04-26

申请号：US14259530

申请日：2014-04-23

Applicant: LSI Corporation

Inventor： Steven D. Cate ,  John W. Osenbach

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/00 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/37 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2224/03

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract translation: 一种在倒装芯片上形成金属柱的工艺。 支柱以及一层焊料将用于将器件上的管芯焊盘与衬底上相应的衬底焊盘接合。 在器件上沉积光致抗蚀剂，并且通过在光致抗蚀剂中形成第一直径的开口来暴露器件上的第一组裸片焊盘。 通过将金属电镀到暴露的裸片上而形成第一直径的支柱。 然后沉积在第一光致抗蚀剂上的第二光致抗蚀剂覆盖第一直径的柱。 在第一和第二光致抗蚀剂中形成第二直径的开口以暴露第二组裸片。 通过将金属电镀在暴露的裸片上形成第二直径的支柱。 然后将光致抗蚀剂与用作电镀工艺的一部分的器件上的导电层一起除去。

公开(公告)号：US20160079193A1

公开(公告)日：2016-03-17

申请号：US14484313

申请日：2014-09-12

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0544 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.

Abstract translation: 一种包括形成铜柱的方法，在铜柱的顶表面和侧壁上电镀金属层，并且在铜柱的顶表面上方与金属层直接接触地电镀金属帽。 该方法还包括通过在非还原环境中加热金属层和铜柱形成金属间化合物，金属间化合物包括铜柱和金属层的元素，其中熔融的焊料将润湿金属帽并且不会湿润 到金属间化合物。

公开(公告)号：US09159660B2

公开(公告)日：2015-10-13

申请号：US14042979

申请日：2013-10-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US09142521B2

公开(公告)日：2015-09-22

申请号：US14153126

申请日：2014-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei Sen Chang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/01051 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.

Abstract translation: 形成集成电路器件的方法包括形成覆盖凸块下的冶金（UBM）层的掩模层，其中掩模层包括与UBM层相邻的第一部分和覆盖第一部分的第二部分。 该方法还包括在掩模层中形成开口以暴露UBM层的一部分。 该方法还包括在掩模层的开口中形成导电层，电连接到UBM层的暴露部分。 该方法还包括去除掩模层的第二部分以暴露导电层的上部。 该方法还包括在导电层的暴露的上部形成阻挡层。

公开(公告)号：US20140264890A1

公开(公告)日：2014-09-18

申请号：US13834058

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dirk Breuer ,  Frank Kuechenmeister ,  Jens Paul ,  Kashi Vishwanath Machani

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/207 ,  H01L2924/00

Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.

Abstract translation: 本文公开的一个说明性支柱包括导电耦合到集成电路的接合焊盘和包括导体耦合到接合焊盘的基座的支柱，其中基部具有第一横向尺寸，并且导电耦合到基座 ，其中所述上部具有小于所述第一横向尺寸的第二横向尺寸。 本文公开的形成柱的方法包括形成基底，使得其与集成电路产品上的接合焊盘导电耦合，并且在形成基底之后，形成上部，使得其与基底导电耦合。

公开(公告)号：US08829688B2

公开(公告)日：2014-09-09

申请号：US13680931

申请日：2012-11-19

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Yoshihiro Machida

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/488 ,  H01L21/768 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11831 ,  H01L2224/11906 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2224/11

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract translation: 半导体器件包括布置有电极焊盘的半导体元件。 布线基板包括分别布置成与电极焊盘相对应的连接焊盘。 柱状电极端子分别形成在半导体元件的电极焊盘上。 焊接点电连接每个电极端子的远端部分和布线基板上的对应的连接焊盘。 每个电极端子包括连接到相应的电极焊盘的基部和形成在远端部分中的引导件。 如上所述，导向件具有比基部更小的横截面面积。 引导件具有圆周，并且基部具有与引导件的圆周部分齐平的圆周。 引导件被形成以引导焊料朝向引导件的圆周。

公开(公告)号：US20140027905A1

公开(公告)日：2014-01-30

申请号：US14042979

申请日：2013-10-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US20130249081A1

公开(公告)日：2013-09-26

申请号：US13426857

申请日：2012-03-22

Applicant: Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/58 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract translation: 制造细间距凸块的方法包括提供硅衬底; 在硅衬底上形成具有多个第一区和多个第二区的含钛金属层; 在含钛金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层; 形成具有多个第一顶表面和多个第一环表面的多个铜凸块; 加热光致抗蚀剂层以形成多个主体部分和可移除部分; 蚀刻光致抗蚀剂层; 在所述含钛金属层，所述第一顶表面和所述第一环表面上形成多个凸块保护层，所述凸块保护层中的每一个包括凸起覆盖部分; 在凸点覆盖部分处镀覆多个金层; 最终，移除第二区域以使得每个第一区域形成凸起下的冶金层。

公开(公告)号：US08530344B1

公开(公告)日：2013-09-10

申请号：US13426857

申请日：2012-03-22

Applicant: Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC: H01L21/44

CPC classification number: H01L23/58 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract translation: 制造细间距凸块的方法包括提供硅衬底; 在硅衬底上形成具有多个第一区和多个第二区的含钛金属层; 在含钛金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层; 形成具有多个第一顶表面和多个第一环表面的多个铜凸块; 加热光致抗蚀剂层以形成多个主体部分和可移除部分; 蚀刻光致抗蚀剂层; 在所述含钛金属层，所述第一顶表面和所述第一环表面上形成多个凸块保护层，所述凸块保护层中的每一个包括凸起覆盖部分; 在凸点覆盖部分处镀覆多个金层; 最终，移除第二区域以使得每个第一区域形成凸起下的冶金层。