公开(公告)号：US09881892B2

公开(公告)日：2018-01-30

申请号：US15412072

申请日：2017-01-23

申请人： Novatek Microelectronics Corp.

发明人： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L27/02 ,  H01L23/50

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

摘要： An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

公开(公告)号：US20170133343A1

公开(公告)日：2017-05-11

申请号：US15412072

申请日：2017-01-23

申请人： Novatek Microelectronics Corp.

发明人： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC分类号： H01L23/00 ,  H01L23/50 ,  H01L27/02

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

摘要： An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

公开(公告)号：US09576891B1

公开(公告)日：2017-02-21

申请号：US14872692

申请日：2015-10-01

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Qian Tao ,  Richard Lum Kok Keong ,  Boon Keat Tan

IPC分类号： H01L29/00 ,  H01L23/522

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/46 ,  H01L25/0655 ,  H01L29/0649 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2924/00014 ,  H01L2224/45099

摘要： An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.

摘要翻译： 一种用于将第一电路的第一信号与所公开的第二电路隔离的隔离装置。 隔离装置可以具有衬底和设置在衬底上的多个金属层。 多个金属层具有最远离衬底设置的最顶层金属层和最靠近衬底形成的第一互连金属层。 第一互连金属层设置在远离基板的第一距离处，而最顶层金属层设置在隔离距离远离最靠近最顶层金属层形成的第一相邻金属层。 最顶层金属层的一部分形成第一板。 第一板被配置为将第一信号从第一电路传输到连接到第二电路但与第一板电隔离的第二板。

公开(公告)号：US20160141284A1

公开(公告)日：2016-05-19

申请号：US14897362

申请日：2013-08-23

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Mikio ISHIHARA ,  Kazuaki HIYAMA ,  Tatsuya KAWASE ,  Tsuyoshi OSAGA

IPC分类号： H01L27/02 ,  H01L23/34 ,  H01L27/06 ,  H01L23/00

CPC分类号： H01L27/0251 ,  H01L23/34 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0828 ,  H03K2017/0806 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.

摘要翻译： 晶体管（2）设置在半导体衬底（8）上。 用于监测半导体衬底（8）的上表面的温度的温度检测二极管（4）设置在半导体衬底（8）上。 外部电极（7）共同连接到晶体管（2）的发射极（E）和温度检测二极管（4）的阴极（K）。 因此，可以去除用于温度检测二极管（4）的阴极（K）的外部电极，因此可以减小装置的尺寸并且在组装的容易性方面得到改进。

公开(公告)号：US08446726B2

公开(公告)日：2013-05-21

申请号：US12914171

申请日：2010-10-28

申请人： Ralf Schloerke ,  Thilo Stolze

发明人： Ralf Schloerke ,  Thilo Stolze

IPC分类号： H05K7/20 ,  H01L23/34 ,  F28F7/00

CPC分类号： H01L23/24 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3735 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L2224/8584 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor module includes a module housing with a sealing ring on its top side. The sealing ring, in co-operation with the module housing and a printed circuit board attached to the power semiconductor module, hermetically seals feed-through locations at the top side of the module housing for feeding through electric terminals of the power semiconductor module. On the bottom side of the module housing a sealing ring hermetically seals the bottom side of the module housing.

摘要翻译： 功率半导体模块包括在其顶侧具有密封环的模块壳体。 与模块壳体配合的密封环和连接到功率半导体模块的印刷电路板密封地密封模块壳体顶侧的馈通位置，以通过功率半导体模块的电端子供电。 在密封环的模块的底侧上，密封环密封模块壳体的底侧。

公开(公告)号：US08253247B2

公开(公告)日：2012-08-28

申请号：US12756208

申请日：2010-04-08

申请人： Noriko Numata ,  Hiroshi Sato ,  Toru Ueguri

发明人： Noriko Numata ,  Hiroshi Sato ,  Toru Ueguri

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L29/7813 ,  H01L23/4824 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/77 ,  H01L24/78 ,  H01L24/84 ,  H01L24/85 ,  H01L24/97 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/7811 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48132 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

摘要： In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.

摘要翻译： 在涉及将金属带接合到半导体芯片的焊盘的步骤的半导体器件的制造方法中，即使当金属带变薄时，也可以确保金属带的断裂，同时确保接合强度，同时尺寸减小 半导体芯片。 通过使楔形工具的压接面与Al带压接，同时对位于焊盘上的带施加超声波振动，将Al带接合到半导体芯片的焊盘，在两端部预先形成有凹部10a 分别与楔形工具接合的Al带的宽度方向上的两个端部应接触楔形工具的压接表面。

公开(公告)号：US20170011985A1

公开(公告)日：2017-01-12

申请号：US15206303

申请日：2016-07-10

申请人： Semikron Elektronik GmbH & Co., KG

发明人： Christian WALTER

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/043 ,  G01R19/00 ,  H05K5/02 ,  H01L23/00 ,  H01L23/473 ,  H01L23/373 ,  H05K5/00

CPC分类号： H01L23/3675 ,  G01R19/0092 ,  H01L23/043 ,  H01L23/055 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/50 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2924/00014 ,  H05K7/1432 ,  H05K7/209 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： A power electronics module having a base plate, a circuit carrier arranged on the base plate and a plurality of conductor tracks which are electrically insulated from the base plate. A power semiconductor component is arranged on one of the conductor tracks, and has a load connection element. In this case, the base plate has a substantially continuous first recess and the circuit carrier has a substantially continuous second recess, wherein the first and second recesses are arranged such that they are in alignment with one another. The load connection element has a first contact device which is in electrically conductive contact with a contact area of that side of the conductor track which is averted from the base plate, a second contact device for externally making contact with the circuit carrier, and a connecting section, which extends through the first and second recesses, between the first and second contact devices.

摘要翻译： 一种功率电子模块，具有基板，布置在基板上的电路载体和与基板电绝缘的多个导体轨道。 功率半导体部件布置在一个导体轨道上，并具有负载连接元件。 在这种情况下，基板具有基本上连续的第一凹部，并且电路载体具有基本上连续的第二凹部，其中第一凹部和第二凹部被布置成使得它们彼此对准。 负载连接元件具有第一接触装置，其与从基板避开的导体轨道的该侧的接触区域导电接触，用于外部与电路载体接触的第二接触装置和连接 其在第一和第二接触装置之间延伸穿过第一和第二凹部。

公开(公告)号：US09530766B2

公开(公告)日：2016-12-27

申请号：US14897362

申请日：2013-08-23

申请人： Mitsubishi Electric Corporation

发明人： Mikio Ishihara ,  Kazuaki Hiyama ,  Tatsuya Kawase ,  Tsuyoshi Osaga

IPC分类号： H01L29/74 ,  H01L27/02 ,  H03K17/082 ,  H01L23/00 ,  H01L23/34 ,  H01L27/06 ,  H03K17/08

CPC分类号： H01L27/0251 ,  H01L23/34 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0828 ,  H03K2017/0806 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.

摘要翻译： 晶体管（2）设置在半导体衬底（8）上。 用于监测半导体衬底（8）的上表面的温度的温度检测二极管（4）设置在半导体衬底（8）上。 外部电极（7）共同连接到晶体管（2）的发射极（E）和温度检测二极管（4）的阴极（K）。 因此，可以去除用于温度检测二极管（4）的阴极（K）的外部电极，因此可以减小装置的尺寸并且在组装的容易性方面得到改进。

公开(公告)号：US20150287686A1

公开(公告)日：2015-10-08

申请号：US14740286

申请日：2015-06-16

申请人： Novatek Microelectronics Corp.

发明人： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC分类号： H01L23/00 ,  H01L27/02

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

摘要： An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

摘要翻译： 提供了包括半导体衬底，第一焊盘结构，第二接合焊盘结构和内部接合线的集成电路器件。 第一焊盘结构设置在半导体衬底的表面上并暴露在半导体衬底的外部。 第二焊盘结构设置在半导体衬底的表面上并暴露在半导体衬底的外部。 第一焊盘结构通过内部接合线电耦合到第二接合焊盘结构。 具有更好的电气性能的集成电路器件通过消除电源轨迹或接地轨迹中的内部电阻下降以及提高集成电路器件的信号完整性来提供。

公开(公告)号：US09118126B2

公开(公告)日：2015-08-25

申请号：US13739422

申请日：2013-01-11

申请人： International Rectifier Corporation

发明人： Hsueh-Rong Chang

IPC分类号： H01L23/48 ,  H01L29/66 ,  H01R13/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L29/739

CPC分类号： H01R13/10 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L25/072 ,  H01L29/7393 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/37639 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84011 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/09511 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3641 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

摘要： According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

摘要翻译： 根据一个所公开的实施例，功率半导体封装包括驻留在封装衬底上的绝缘栅双极晶体管（IGBT），其中IGBT包括位于IGBT顶部并连接到IGBT的多个可焊接前金属（SFM） IGBT的发射极。 功率半导体封装还包括将多个SFM涂覆的发射极区段耦合到封装衬底上的发射极焊盘的导电夹。 此外，功率半导体封装包括耦合到IGBT的栅极的封装衬底上的栅极焊盘，位于IGBT下方并耦合到IGBT的集电极的封装衬底上的集电极焊盘，以及发射极端子，集电极端子 以及封装衬底的栅极端子，其分别被引导到发射极焊盘，集电极焊盘和栅极焊盘。