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公开(公告)号：US11694960B2
公开(公告)日：2023-07-04
申请号：US17410716
申请日：2021-08-24
Applicant: Intel Corporation
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L23/00 , H01L25/065 , H05K1/18 , H01L23/532 , H01L25/18 , H05K3/34
CPC classification number: H01L23/5381 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/53238 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H05K1/185 , H01L24/13 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/171 , H01L2224/1703 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/8147 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/00014 , H01L2924/0103 , H01L2924/0105 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01072 , H01L2924/0496 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K3/3436 , H05K2201/10363 , H01L2224/81815 , H01L2924/00014 , H01L2224/131 , H01L2924/014 , H01L2224/81455 , H01L2924/00014 , H01L2224/81481 , H01L2924/00014 , H01L2224/81487 , H01L2924/04953 , H01L2224/81487 , H01L2924/04941 , H01L2224/81466 , H01L2924/01074 , H01L2224/81463 , H01L2924/01072 , H01L2224/81479 , H01L2924/00014 , H01L2224/8147 , H01L2924/00014 , H01L2224/81472 , H01L2924/00014 , H01L2224/81484 , H01L2924/00014 , H01L2224/81487 , H01L2924/0543 , H01L2924/01049 , H01L2224/81487 , H01L2924/0481 , H01L2924/01029 , H01L2224/81487 , H01L2924/0496 , H01L2924/01074 , H01L2224/171 , H01L2924/00012 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
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公开(公告)号：US12132002B2
公开(公告)日：2024-10-29
申请号：US18139862
申请日：2023-04-26
Applicant: Intel Corporation
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L23/00 , H01L23/532 , H01L25/065 , H01L25/18 , H05K1/18 , H05K3/34
CPC classification number: H01L23/5381 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H05K1/185 , H01L24/13 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/0496 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K3/3436 , H05K2201/10363 , H01L2224/81815 , H01L2924/00014 , H01L2224/131 , H01L2924/014 , H01L2224/81455 , H01L2924/00014 , H01L2224/81481 , H01L2924/00014 , H01L2224/81487 , H01L2924/04953 , H01L2224/81487 , H01L2924/04941 , H01L2224/81466 , H01L2924/01074 , H01L2224/81463 , H01L2924/01072 , H01L2224/81479 , H01L2924/00014 , H01L2224/8147 , H01L2924/00014 , H01L2224/81472 , H01L2924/00014 , H01L2224/81484 , H01L2924/00014 , H01L2224/81487 , H01L2924/0543 , H01L2924/01049 , H01L2224/81487 , H01L2924/0481 , H01L2924/01029 , H01L2224/81487 , H01L2924/0496 , H01L2924/01074 , H01L2224/171 , H01L2924/00012 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
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公开(公告)号：US20120236230A1
公开(公告)日：2012-09-20
申请号：US13510721
申请日：2010-09-15
Applicant: Hiroki Nakahama , Takashi Matsui , Takeshi Horiguchi , Motoji Shiota
Inventor： Hiroki Nakahama , Takashi Matsui , Takeshi Horiguchi , Motoji Shiota
IPC: G02F1/1335 , H01J9/00 , H05K13/04 , H05K1/18
CPC classification number: G02F1/1345 , G02F2001/13456 , H01L23/4985 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/02185 , H01L2224/0401 , H01L2224/05567 , H01L2224/1146 , H01L2224/13006 , H01L2224/13019 , H01L2224/16 , H01L2224/16013 , H01L2224/16112 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17107 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81385 , H01L2224/81395 , H01L2224/81424 , H01L2224/81481 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15788 , Y10T156/10 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/0665 , H01L2924/00 , H01L2224/05552
Abstract: Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.
Abstract translation: 公开了一种器件基板，其中在其表面上形成有端子（24）的绝缘层（60）形成在除了显示部分之外的玻璃基板（20）的整个表面上，因此，边界（外围 绝缘层（60）不接近设置有NCF（81）的区域，即靠近LSI芯片（40）的区域。 这防止绝缘层（60）被NCF（81）从其边界剥离，从而防止端子（24）断裂。 此外，端子（24）和突起电极（40a）通过绝缘层（60）的弹性而彼此永久地压接，并且可以确保其间的稳定的电连接。
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公开(公告)号：US20170207168A1
公开(公告)日：2017-07-20
申请号：US15478858
申请日：2017-04-04
Applicant: INTEL CORPORATION
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L25/18 , H01L25/065 , H01L23/532 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/4821 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K1/185 , H05K3/3436 , H05K2201/10363 , H01L2924/00014 , H01L2924/014 , H01L2924/04953 , H01L2924/04941 , H01L2924/01074 , H01L2924/01072 , H01L2924/0543 , H01L2924/01049 , H01L2924/0481 , H01L2924/0496 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
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公开(公告)号：US20150364423A1
公开(公告)日：2015-12-17
申请号：US14836906
申请日：2015-08-26
Applicant: INTEL CORPORATION
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L25/18 , H01L23/532
CPC classification number: H01L23/5381 , H01L23/4821 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K1/185 , H05K3/3436 , H05K2201/10363 , H01L2924/00014 , H01L2924/014 , H01L2924/04953 , H01L2924/04941 , H01L2924/01074 , H01L2924/01072 , H01L2924/0543 , H01L2924/01049 , H01L2924/0481 , H01L2924/0496 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09147663B2
公开(公告)日：2015-09-29
申请号：US13903828
申请日：2013-05-28
Applicant: INTEL CORPORATION
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/00 , H01L23/538 , H01L23/482 , H01L25/065
CPC classification number: H01L23/5381 , H01L23/4821 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K1/185 , H05K3/3436 , H05K2201/10363 , H01L2924/00014 , H01L2924/014 , H01L2924/04953 , H01L2924/04941 , H01L2924/01074 , H01L2924/01072 , H01L2924/0543 , H01L2924/01049 , H01L2924/0481 , H01L2924/0496 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20240071990A1
公开(公告)日：2024-02-29
申请号：US17896030
申请日：2022-08-25
Applicant: Micron Technology, Inc.
Inventor： Kelvin Tan Aik Boo , Seng Kim Ye , Hong Wan Ng , Ling Pan , See Hiong Leow
IPC: H01L23/00 , H01L21/48 , H01L23/498
CPC classification number: H01L24/81 , H01L21/4846 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L2224/13082 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13169 , H01L2224/13173 , H01L2224/13176 , H01L2224/13178 , H01L2224/1318 , H01L2224/13181 , H01L2224/13183 , H01L2224/13184 , H01L2224/16238 , H01L2224/81385 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81469 , H01L2224/81473 , H01L2224/81476 , H01L2224/81478 , H01L2224/8148 , H01L2224/81481 , H01L2224/81483 , H01L2224/81484 , H01L2224/81815 , H01L2924/3841
Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
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公开(公告)号：US11749534B1
公开(公告)日：2023-09-05
申请号：US17957683
申请日：2022-09-30
Applicant: Deca Technologies USA, Inc.
Inventor： Robin Davis , Paul R. Hoffman , Clifford Sandstrom , Timothy L. Olson
CPC classification number: H01L21/4839 , H01L21/561 , H01L21/568 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13147 , H01L2224/16245 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81457 , H01L2224/81466 , H01L2224/81469 , H01L2224/81481 , H01L2224/81484
Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.
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公开(公告)号：US20190013271A1
公开(公告)日：2019-01-10
申请号：US16129577
申请日：2018-09-12
Applicant: INTEL CORPORATION
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L23/00 , H01L23/482 , H01L25/18 , H01L23/532
CPC classification number: H01L23/5381 , H01L23/4821 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/0496 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K1/185 , H05K3/3436 , H05K2201/10363 , H01L2924/014 , H01L2924/04953 , H01L2924/04941 , H01L2924/01074 , H01L2924/0543 , H01L2924/01049 , H01L2924/0481 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
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公开(公告)号：US09640485B2
公开(公告)日：2017-05-02
申请号：US14836906
申请日：2015-08-26
Applicant: INTEL CORPORATION
Inventor： Yueli Liu , Qinglei Zhang , Amanda E. Schuckman , Rui Zhang
IPC: H01L23/538 , H01L23/00 , H01L23/482 , H01L25/065 , H05K1/18 , H01L23/532 , H01L25/18 , H05K3/34
CPC classification number: H01L23/5381 , H01L23/4821 , H01L23/53238 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/27 , H01L24/33 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/171 , H01L2224/2746 , H01L2224/32225 , H01L2224/3303 , H01L2224/33505 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81455 , H01L2224/81463 , H01L2224/81466 , H01L2224/8147 , H01L2224/81472 , H01L2224/81479 , H01L2224/81481 , H01L2224/81484 , H01L2224/81487 , H01L2224/81815 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H05K1/185 , H05K3/3436 , H05K2201/10363 , H01L2924/00014 , H01L2924/014 , H01L2924/04953 , H01L2924/04941 , H01L2924/01074 , H01L2924/01072 , H01L2924/0543 , H01L2924/01049 , H01L2924/0481 , H01L2924/0496 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
