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公开(公告)号:US20180211912A1
公开(公告)日:2018-07-26
申请号:US15640949
申请日:2017-07-03
发明人: Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Jing-Cheng Lin , Hung-Jui Kou
IPC分类号: H01L23/522 , H01L23/538 , H01L23/498 , H01L23/48 , H01L23/00 , H01L21/48 , H01L21/768
CPC分类号: H01L21/76805 , H01L21/4853 , H01L21/486 , H01L21/76813 , H01L23/481 , H01L23/49827 , H01L23/5226 , H01L23/5384 , H01L24/13 , H01L24/24 , H01L24/27 , H01L24/28 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/82 , H01L2224/04042 , H01L2224/24147 , H01L2224/244 , H01L2224/29144 , H01L2224/29147 , H01L2224/32145 , H01L2224/32265 , H01L2224/73215 , H01L2224/73217 , H01L2224/73227 , H01L2224/73267 , H01L2224/82051 , H01L2224/821 , H01L2224/82951 , H01L2224/83191 , H01L2224/83815 , H01L2224/83895
摘要: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
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公开(公告)号:US20160020188A1
公开(公告)日:2016-01-21
申请号:US14868090
申请日:2015-09-28
申请人: Invensas Corporation
发明人: Jeffrey S. Leal
IPC分类号: H01L23/00 , H01L21/324 , H01L21/31 , H01L21/768 , H01L25/00
CPC分类号: H01L24/82 , H01L21/02282 , H01L21/02288 , H01L21/31 , H01L21/324 , H01L21/56 , H01L21/76801 , H01L21/76828 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/0657 , H01L25/50 , H01L2224/19 , H01L2224/24145 , H01L2224/76155 , H01L2224/82051 , H01L2224/82101 , H01L2224/82102 , H01L2224/82355 , H01L2225/06524 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
摘要翻译: 使用添加剂方法来电绝缘模具堆叠上的选定表面区域; 以及用于在管芯堆叠中电互连管芯的方法包括用于电绝缘管芯的选定表面区域的添加工艺。 根据本发明不是绝缘的区域可用于使用以可流动形式施加的导电材料进行电连接以制造导电迹线。
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公开(公告)号:US20170171958A1
公开(公告)日:2017-06-15
申请号:US14965039
申请日:2015-12-10
发明人: Tse Nga Ng , Ping Mei , Brent S. Krusor , Gregory L. Whiting , Steven E. Ready , Janos Veres
CPC分类号: H05K1/028 , H01L21/568 , H01L23/3107 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/76 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24991 , H01L2224/76151 , H01L2224/76155 , H01L2224/76252 , H01L2224/82051 , H01L2224/82181 , H01L2224/8285 , H01L2224/82986 , H05K1/0326 , H05K1/185 , H05K3/14 , Y10T29/4913
摘要: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.
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公开(公告)号:US20160330837A1
公开(公告)日:2016-11-10
申请号:US15105350
申请日:2014-12-19
IPC分类号: H05K1/11 , H01L21/48 , H01L23/538 , H05K3/46 , H05K3/30 , H01L21/56 , H05K1/03 , H01L23/14 , H05K1/18
CPC分类号: H05K1/118 , H01L21/4853 , H01L21/4857 , H01L21/56 , H01L23/145 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/82 , H01L33/62 , H01L2224/24011 , H01L2224/2402 , H01L2224/24101 , H01L2224/24137 , H01L2224/25175 , H01L2224/82005 , H01L2224/82051 , H01L2224/82106 , H01L2224/82951 , H01L2224/97 , H01L2933/0066 , H05K1/025 , H05K1/0393 , H05K1/189 , H05K3/303 , H05K3/4644 , H05K3/465 , H05K3/4682 , H05K2201/0154 , H05K2201/0162 , H05K2201/0209 , H05K2201/026 , H05K2201/10037 , H05K2201/10106 , H05K2201/10121 , H05K2201/10151 , H05K2201/10166 , H05K2201/10174 , H05K2201/10522 , H05K2203/0173 , H05K2203/1316 , H05K2203/1469 , H05K3/467 , H01L2224/82
摘要: Disclosed are highly scalable fabrication methods for producing electronic circuits, devices, and systems. In one aspect, a fabrication method includes attaching an electronic component at a location on a substrate including a flexible and electrically insulative material; forming a template to encase the electronic component by depositing a material in a phase to conform on the surfaces of the electronic component and the substrate, and causing the material to change to solid form; and producing a circuit or electronic device by forming openings in the substrate to expose conductive portions of the electronic component, creating electrical interconnections coupled to at least some of the conductive portions in a selected arrangement on the substrate, and depositing a layer of an electrically insulative and flexible material over the electrical interconnections on the substrate to form a flexible base of the circuit, in which the produced circuit or electronic device is encased.
摘要翻译: 公开了用于生产电子电路,设备和系统的高度可扩展的制造方法。 一方面,一种制造方法,包括在包括柔性和电绝缘材料的基板上的位置处附接电子部件; 形成模板以通过在相位上沉积材料以使电子部件和基板的表面相符合并使材料变为固体形式来包住电子部件; 以及通过在所述衬底中形成开口以暴露所述电子部件的导电部分来产生电路或电子器件,从而在所述衬底上以所选择的布置形成耦合到至少一些所述导电部分的电互连,以及沉积电绝缘层 以及在基板上的电互连上的柔性材料以形成电路的柔性基座,其中所生产的电路或电子设备被封装在该基板中。
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公开(公告)号:US09147583B2
公开(公告)日:2015-09-29
申请号:US12913529
申请日:2010-10-27
申请人: Jeffrey S. Leal
发明人: Jeffrey S. Leal
IPC分类号: H01L21/31 , H01L21/469 , H01L21/56 , H01L21/02 , H01L23/00 , H01L25/065
CPC分类号: H01L24/82 , H01L21/02282 , H01L21/02288 , H01L21/31 , H01L21/324 , H01L21/56 , H01L21/76801 , H01L21/76828 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/0657 , H01L25/50 , H01L2224/19 , H01L2224/24145 , H01L2224/76155 , H01L2224/82051 , H01L2224/82101 , H01L2224/82102 , H01L2224/82355 , H01L2225/06524 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
摘要翻译: 使用添加剂方法来电绝缘模具堆叠上的选定表面区域; 以及用于在管芯堆叠中电互连管芯的方法包括用于电绝缘管芯的选定表面区域的添加工艺。 根据本发明不是绝缘的区域可用于使用以可流动形式施加的导电材料进行电连接以制造导电迹线。
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公开(公告)号:US20180114773A1
公开(公告)日:2018-04-26
申请号:US15704984
申请日:2017-09-14
发明人: Chin Tien Chiu , Tiger Tai , Ken Qian , CC Liao , Hem Takiar , Gursharan Singh
IPC分类号: H01L25/065 , H01L25/00
CPC分类号: H01L25/0652 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/82 , H01L25/50 , H01L2224/02371 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/16137 , H01L2224/16145 , H01L2224/24051 , H01L2224/24105 , H01L2224/24147 , H01L2224/244 , H01L2224/245 , H01L2224/2512 , H01L2224/25175 , H01L2224/2518 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/73207 , H01L2224/73209 , H01L2224/73227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73267 , H01L2224/82051 , H01L2224/82106 , H01L2224/82948 , H01L2225/06506 , H01L2225/06513 , H01L2225/06551 , H01L2225/06555 , H01L2924/01079 , H01L2924/01029 , H01L2924/01013 , H01L2924/00012 , H01L2924/00014
摘要: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
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公开(公告)号:US09490230B2
公开(公告)日:2016-11-08
申请号:US14868090
申请日:2015-09-28
申请人: Invensas Corporation
发明人: Jeffrey S. Leal
IPC分类号: H01L21/31 , H01L21/469 , H01L23/00 , H01L21/02 , H01L21/56 , H01L25/065 , H01L21/324 , H01L21/768 , H01L25/00
CPC分类号: H01L24/82 , H01L21/02282 , H01L21/02288 , H01L21/31 , H01L21/324 , H01L21/56 , H01L21/76801 , H01L21/76828 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/0657 , H01L25/50 , H01L2224/19 , H01L2224/24145 , H01L2224/76155 , H01L2224/82051 , H01L2224/82101 , H01L2224/82102 , H01L2224/82355 , H01L2225/06524 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
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公开(公告)号:US20130241077A1
公开(公告)日:2013-09-19
申请号:US13423951
申请日:2012-03-19
申请人: Edward Fuergut , Joachim Mahler , Khalil Hosseini
发明人: Edward Fuergut , Joachim Mahler , Khalil Hosseini
CPC分类号: H01L21/568 , H01L21/56 , H01L21/561 , H01L23/3128 , H01L23/492 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/072 , H01L25/16 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/05559 , H01L2224/05567 , H01L2224/05572 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/82007 , H01L2224/82047 , H01L2224/82051 , H01L2224/96 , H01L2924/00014 , H01L2924/01322 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/181 , H01L2924/18162 , H01L2924/19105 , H01L2924/00 , H01L2224/11 , H01L2924/014 , H01L2224/05552
摘要: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.
摘要翻译: 在一个实施例中,形成半导体封装的方法包括将第一裸片和第二裸片放置在载体上。 第一和第二管芯中的至少一个被封装材料覆盖以形成具有顶表面和相对底表面的密封剂。 密封剂从底表面变薄以暴露第一模具的第一表面而不暴露第二模具。 选择性地蚀刻第一裸片的暴露的第一表面以暴露第一裸片的第二表面。 背面导电层形成为与第一表面接触。 第二模具通过密封剂的第一部分与背侧导电层分离。
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公开(公告)号:US20110266684A1
公开(公告)日:2011-11-03
申请号:US12913529
申请日:2010-10-27
申请人: Jeffrey S. Leal
发明人: Jeffrey S. Leal
IPC分类号: H01L21/28 , H01L21/31 , H01L23/48 , H01L21/768
CPC分类号: H01L24/82 , H01L21/02282 , H01L21/02288 , H01L21/31 , H01L21/324 , H01L21/56 , H01L21/76801 , H01L21/76828 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/0657 , H01L25/50 , H01L2224/19 , H01L2224/24145 , H01L2224/76155 , H01L2224/82051 , H01L2224/82101 , H01L2224/82102 , H01L2224/82355 , H01L2225/06524 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
摘要翻译: 使用添加剂方法来电绝缘模具堆叠上的选定表面区域; 以及用于在管芯堆叠中电互连管芯的方法包括用于电绝缘管芯的选定表面区域的添加工艺。 根据本发明不是绝缘的区域可用于使用以可流动形式施加的导电材料进行电连接以制造导电迹线。
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公开(公告)号:US20180254258A1
公开(公告)日:2018-09-06
申请号:US15759735
申请日:2016-09-14
申请人: 3DIS Technologies
发明人: Ayad Ghannam
CPC分类号: H01L24/82 , H01L21/4857 , H01L23/49822 , H01L24/24 , H01L28/10 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24146 , H01L2224/24226 , H01L2224/24265 , H01L2224/24991 , H01L2224/24998 , H01L2224/82051 , H01L2224/821 , H01L2224/82101 , H01L2924/19011 , H01L2924/19042 , H01L2924/19104 , H05K3/4661
摘要: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 μm and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.
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