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公开(公告)号：US20240347515A1
公开(公告)日：2024-10-17
申请号：US18757531
申请日：2024-06-28
Inventor： Ming-Fa Chen , Sung-Feng Yeh , Tzuan-Horng Liu , Chao-Wen Shih
IPC: H01L25/065 , H01L23/31 , H01L23/522 , H01L23/528 , H01L23/538 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/29
CPC classification number: H01L25/0657 , H01L23/3128 , H01L23/3185 , H01L23/3192 , H01L23/5226 , H01L23/5283 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/50 , H01L21/561 , H01L23/291 , H01L24/97
Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.
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公开(公告)号：US12113010B2
公开(公告)日：2024-10-08
申请号：US17754238
申请日：2019-11-15
Applicant: Mitsubishi Electric Corporation
Inventor： Shigeto Fujita , Tetsuya Matsuda
IPC: H01L23/50 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/065 , H01L25/07 , H01L25/075
CPC classification number: H01L23/50 , H01L21/56 , H01L23/3107 , H01L24/37 , H01L24/40 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/072 , H01L25/0753 , H01L2924/181
Abstract: A semiconductor device includes a plurality of semiconductor chips, an insulating part, a first electrode, a second electrode, a first bus bar, and a second bus bar. The insulating part surrounds the semiconductor chips. The first electrode is in pressure contact with the semiconductor chips. The semiconductor chips are sandwiched between the first electrode and the second electrode in a first direction. The second electrode is in pressure contact with the semiconductor chips. The first bus bar is connected to the first electrode. The second bus bar is connected to the second electrode. The first bus bar and the second bus bar sandwich the insulating part in a second direction intersecting the first direction.
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公开(公告)号：US20240334608A1
公开(公告)日：2024-10-03
申请号：US18740889
申请日：2024-06-12
Inventor： Chia-Kuei HSU , Ming-Chih YEW , Po-Chen LAI , Po-Yao LIN , Shin-Puu JENG
IPC: H05K1/18 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065 , H05K3/28 , H05K3/34
CPC classification number: H05K1/181 , H01L25/0655 , H05K3/284 , H01L23/3185 , H01L23/49811 , H01L23/5383 , H01L24/73 , H01L24/92 , H01L24/97 , H01L2224/73204 , H01L2224/92125 , H01L2224/95001 , H05K3/3436 , H05K2201/10378 , H05K2201/10727 , H05K2201/10734 , H05K2201/10977 , H05K2203/107
Abstract: A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.
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公开(公告)号：US20240321857A1
公开(公告)日：2024-09-26
申请号：US18736766
申请日：2024-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/00 , H01L21/768 , H01L21/78 , H01L23/00 , H01L25/065
CPC classification number: H01L25/50 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/80 , H01L24/94 , H01L24/97 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541
Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US12094843B2
公开(公告)日：2024-09-17
申请号：US17817481
申请日：2022-08-04
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： Pandi Chelvam Marimuthu , Andy Chang Bum Yong , Aung Kyaw Oo , Yaojian Lin
IPC: H01L23/66 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/538 , H01L23/552
CPC classification number: H01L23/66 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5225 , H01L23/528 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L23/3128 , H01L23/49833 , H01L2221/68331 , H01L2221/68345 , H01L2221/68354 , H01L2221/68359 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/83 , H01L2224/83005 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/3025 , H01L2924/3511
Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
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公开(公告)号：US12094729B2
公开(公告)日：2024-09-17
申请号：US17457719
申请日：2021-12-06
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： Yaojian Lin , Heinz-Peter Wirtz , Seung Wook Yoon , Pandi C. Marimuthu
CPC classification number: H01L21/565 , H01L21/31058 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/28 , H01L23/3114 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L24/11 , H01L24/81 , H01L24/96 , H01L24/97 , H01L21/568 , H01L2224/0508 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/05184 , H01L2224/1134 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/00011 , H01L2924/01322 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10335 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/13091 , H01L2924/00 , H01L2224/97 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/12041 , H01L2924/00 , H01L2924/1306 , H01L2924/00 , H01L2924/01322 , H01L2924/00 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2224/1134 , H01L2924/00014 , H01L2924/00011 , H01L2224/81805
Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.
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公开(公告)号：US12094728B2
公开(公告)日：2024-09-17
申请号：US18324686
申请日：2023-05-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Zi-Jheng Liu , Yu-Hsiang Hu , Jo-Lin Lan , Sih-Hao Liao , Chen-Cheng Kuo , Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu , Meng-Wei Chou
CPC classification number: H01L21/561 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311
Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
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公开(公告)号：US20240304593A1
公开(公告)日：2024-09-12
申请号：US18179126
申请日：2023-03-06
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: H01L24/80 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05647 , H01L2224/06181 , H01L2224/08145 , H01L2224/80009 , H01L2224/80013 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/94 , H01L2224/97 , H01L2225/06565 , H01L2924/01006 , H01L2924/01014 , H01L2924/04642 , H01L2924/0504 , H01L2924/0544 , H01L2924/05494 , H01L2924/059
Abstract: Disclosed herein are processes and methods for direct bonding. In some embodiments, the process includes providing an element having a dielectric bonding surface and one or more conductive features exposed at the dielectric bonding surface, where the dielectric bonding surface has a planarity suitable for direct bonding. The process also includes, after providing the element, exposing the dielectric bonding surface to the products of a water vapor plasma prior to direct bonding the element.
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公开(公告)号：US20240297087A1
公开(公告)日：2024-09-05
申请号：US18115840
申请日：2023-03-01
Inventor： Sheng-Kai CHANG , Chih-Kang Han , Leo Li , Lieh-Chuan Chen , Chien-Li Kuo
IPC: H01L23/16 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L23/16 , H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L21/563 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/96 , H01L2224/97 , H01L2924/1011
Abstract: A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.
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公开(公告)号：US12080702B2
公开(公告)日：2024-09-03
申请号：US17873073
申请日：2022-07-25
Inventor： Hsien-Wei Chen , Jie Chen , Ming-Fa Chen
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L25/00
CPC classification number: H01L25/50 , H01L21/56 , H01L24/06 , H01L24/80 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/06181 , H01L2224/80001
Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.
