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    Cavity structures for MEMS devices
    4.
    发明授权
    Cavity structures for MEMS devices 有权
    MEMS器件的腔结构

    公开(公告)号：US09145292B2

    公开(公告)日：2015-09-29

    申请号：US14281251

    申请日：2014-05-19

    Applicant: Infineon Technologies AG

    Inventor： Bernhard Winkler ,  Andreas Zankl ,  Klemens Pruegl ,  Stefan Kolb

    IPC: H01L21/71 ,  H01L21/205 ,  H01L27/04 ,  H01L27/20 ,  B81B7/02 ,  B81B7/00 ,  B81C1/00 ,  H01L27/06

    CPC classification number: B81B7/008 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C1/00158 ,  B81C1/00246 ,  B81C2203/0707 ,  B81C2203/0714 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L27/0611

    Abstract: Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer. Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated. At the same time, a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective.

    Abstract translation: 实施例涉及MEMS器件，特别是与单个晶片上的相关电气器件集成的MEMS器件。 实施例利用模块化工艺流程概念作为MEMS首要方法的一部分，使得能够使用新颖的腔体密封过程。 因此，通过MEMS处理对电气装置的影响和潜在的有害影响被减少或消除。 同时，提供了一种高度灵活的解决方案，可以实现各种测量原理，包括电容式和压阻式。 因此，可以在提高性能和质量的同时解决各种传感器应用，同时保持成本效益。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20140327074A1

    公开(公告)日：2014-11-06

    申请号：US13875291

    申请日：2013-05-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao

    IPC: H01L27/088 ,  H01L27/06

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

    Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

    Abstract translation: 半导体集成电路包括衬底，形成在衬底上的多栅极晶体管器件和形成在衬底中的n阱电阻器。 衬底包括多个第一隔离结构和至少形成在其中的第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个翅片结构，并且翅片结构彼此平行并且通过第一隔离结构彼此间隔开。 n阱电阻器包括至少一个第一隔离结构。 n阱电阻器和多栅极晶体管器件通过第二隔离结构彼此电隔离。

    METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION
    6.
    发明申请
    METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION 有权
    形成具有IC区域的邻近MEMS区域的方法

    公开(公告)号：US20110156175A1

    公开(公告)日：2011-06-30

    申请号：US12651335

    申请日：2009-12-31

    Applicant: Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

    Inventor： Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

    IPC: H01L29/66 ,  H01L21/02

    CPC classification number: H01L27/0617 ,  B81C1/00246 ,  B81C2203/0742 ,  H01L27/0611

    Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

    Abstract translation: 提出了一种方法，其包括形成具有第一掺杂剂浓度的第一层，所述第一层具有集成电路区域和微机电区域，并且掺杂第一层的微机电区域以具有第二掺杂剂浓度。 该方法包括形成具有覆盖在第一层上的第三掺杂剂浓度的第二层，掺杂覆盖在微机电区域上的第二层以具有第四掺杂剂浓度，在微机电区域中使用第一层 和第二层，并且使用第二层在集成电路区域中形成有源部件。

    Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
    8.
    发明授权
    Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys 失效
    在硅和硅合金中使用互补结场效应晶体管和MOS晶体管的集成电路

    公开(公告)号：US07687834B2

    公开(公告)日：2010-03-30

    申请号：US12263854

    申请日：2008-11-03

    Applicant: Ashok K. Kapoor

    Inventor： Ashok K. Kapoor

    IPC: H01L29/80 ,  H01L21/20

    CPC classification number: H01L29/808 ,  H01L21/2257 ,  H01L27/0611 ,  H01L27/098 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66901 ,  H01L29/7833

    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

    Abstract translation: 本发明描述了使用硅中的结型场效应晶体管构建互补逻辑电路的方法。 本发明理想地适用于深亚微米尺寸，优选低于65nm。 本发明的基础是在增强模式下操作的互补结型场效应晶体管。 JFET的速度功率性能可以与次级70纳米尺寸的CMOS器件相媲美。 然而，JFET的最大电源电压仍然限制在低于内置电位（二极管压降）。 为了满足需要与驱动到更高电压电平的外部电路接口的某些应用，本发明包括在与JFET器件相同的衬底上构建CMOS器件的结构和方法。

    Semiconductor device having IGBT and diode
    10.
    发明申请
    Semiconductor device having IGBT and diode 有权
    具有IGBT和二极管的半导体器件

    公开(公告)号：US20070200138A1

    公开(公告)日：2007-08-30

    申请号：US11709272

    申请日：2007-02-22

    Applicant: Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

    Inventor： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

    IPC: H01L29/74

    CPC classification number: H01L27/0611 ,  H01L29/7395 ,  H01L29/8611

    Abstract: A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

    Abstract translation: 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

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