公开(公告)号：US20180331114A1

公开(公告)日：2018-11-15

申请号：US15969302

申请日：2018-05-02

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati

IPC分类号： H01L27/11514 ,  G11C11/22

CPC分类号： H01L27/11514 ,  G11C11/221 ,  G11C11/2259

摘要： Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

公开(公告)号：US20180323214A1

公开(公告)日：2018-11-08

申请号：US16020712

申请日：2018-06-27

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC分类号： H01L27/11597 ,  H01L29/49 ,  H01L27/11585 ,  H01L21/28 ,  H01L29/51 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/11582

CPC分类号： H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

摘要： A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US20180204845A1

公开(公告)日：2018-07-19

申请号：US15919453

申请日：2018-03-13

申请人： Guobiao ZHANG

发明人： Guobiao ZHANG

IPC分类号： H01L27/112 ,  H01L27/06 ,  H01L27/24 ,  H01L27/11514 ,  H01L27/11597 ,  H01L27/22 ,  H01L23/525 ,  G11C17/16

CPC分类号： H01L27/11206 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/73 ,  H01L23/5252 ,  H01L27/0688 ,  H01L27/11514 ,  H01L27/11597 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV). It comprises horizontal address lines and memory holes there-through, a re-programmable layer and vertical address lines in said memory holes. The re-programmable layer comprises at least first and second sub-layers with different re-programmable materials. The 3D-MTPV comprises no separate diode layer.

公开(公告)号：US10020062B1

公开(公告)日：2018-07-10

申请号：US15792983

申请日：2017-10-25

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Jin-Ho Kim ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11514 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3477 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11582

摘要： A nonvolatile memory device includes well regions formed in a substrate and arranged in a first direction; a memory block including sub blocks which are formed over the substrate and correspond to the well regions, respectively; and bit lines disposed over the memory block, and extending in the first direction. Each of the sub blocks includes channel layers which are formed in a vertical direction between a corresponding well region and the bit lines, word lines and at least one drain select line and at least one erase prevention line, which are stacked over the substrate along the channel layers. In an erase operation, an erase voltage is applied to a well region corresponding to a selected sub block and an erase preventing voltage is applied to an erase prevention line included in an unselected sub block, the erase voltage may be prevented from being transferred to the unselected sub block.

公开(公告)号：US09935114B1

公开(公告)日：2018-04-03

申请号：US15402679

申请日：2017-01-10

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H01L21/02 ,  H01L27/11507

CPC分类号： H01L27/11507 ,  H01L27/11514

摘要： A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.

公开(公告)号：US09928912B2

公开(公告)日：2018-03-27

申请号：US15489272

申请日：2017-04-17

申请人： Hewlett-Packard Development Company, L.P.

发明人： Boon Bing Ng ,  Hang Ru Goy

IPC分类号： G11C11/34 ,  G11C16/08 ,  G11C8/04 ,  G11C16/24 ,  G11C8/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11514 ,  H01L29/423 ,  H01L29/78 ,  G11C8/12 ,  H01L27/11582

CPC分类号： G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

摘要： Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US09741767B2

公开(公告)日：2017-08-22

申请号：US14925254

申请日：2015-10-28

申请人： SK hynix Inc.

发明人： Kyung-Wan Kim

IPC分类号： H01L29/792 ,  H01L27/24 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L27/11514 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/16 ,  H01L27/11597

CPC分类号： H01L27/249 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/2024 ,  G06F2212/60 ,  H01L27/11514 ,  H01L27/11597 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

摘要： Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.

公开(公告)号：US09691973B2

公开(公告)日：2017-06-27

申请号：US14843050

申请日：2015-09-02

申请人： Kabushiki Kaisha Toshiba

发明人： Tsunehiro Ino ,  Riichiro Takaishi ,  Koichi Kato ,  Yasushi Nakasaki ,  Takamitsu Ishihara ,  Daisuke Matsushita

IPC分类号： H01L45/00 ,  G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  C01G25/02 ,  C01G27/00 ,  C01G27/02 ,  H01L29/51

CPC分类号： H01L45/06 ,  C01G25/02 ,  C01G27/00 ,  C01G27/02 ,  G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/1159 ,  H01L27/11597 ,  H01L28/40 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/7843 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.

公开(公告)号：US20160372478A1

公开(公告)日：2016-12-22

申请号：US15257064

申请日：2016-09-06

申请人： Kabushiki Kaisha Toshiba

发明人： Tsunehiro INO ,  Shosuke FUJII ,  Seiji INUMIYA

IPC分类号： H01L27/115 ,  H01L21/3105 ,  H01L29/51 ,  H01L21/02 ,  H01L49/02 ,  H01L29/78

CPC分类号： H01L27/1159 ,  C23C14/083 ,  G11C11/221 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/3105 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/11597 ,  H01L28/40 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

摘要： A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.

摘要翻译： 根据实施例的半导体器件包括第一导电层，第二导电层和包括设置在第一导电层和第二导电层之间的氧化铪的铁电层，铪（Hf）和氧（O）之和在 氧化铪为98原子％以上。

公开(公告)号：US20160118404A1

公开(公告)日：2016-04-28

申请号：US14875744

申请日：2015-10-06

申请人： Haibing Peng

发明人： Haibing Peng

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/16 ,  H01L29/51

CPC分类号： H01L27/11597 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/16 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

摘要： The present invention provides a design of three-dimensional non-volatile ferroelectric random access memory (FeRAM) devices for increasing the storage density. The key components include: (1) FeRAM device structures with (i) field-effect-transistors electrically connected either in series or in parallel as a basic memory group and (ii) a double-gate structure for implementing read/write schemes with full random access to individual memory cells, where one type of gates employs ferroelectrics layers as the gate dielectrics while the other type of gates employs conventional dielectric materials as the gate dielectrics; and (2) FeRAM device structures with stacked ferroelectric-capacitors and field-effect-transistors electrically connected in series as a basic NAND memory group. Example fabrication processes for implementing such three-dimensional FeRAM devices are also provided.

摘要翻译： 本发明提供了一种用于提高存储密度的三维非易失性铁电随机存取存储器（FeRAM）器件的设计。 关键部件包括：（1）FeRAM器件结构，其中（i）场效应晶体管串联或并联电连接为基本存储器组，以及（ii）双栅结构，用于实现具有完整的读/写方案 随机访问单个存储器单元，其中一种类型的栅极使用铁电层作为栅极电介质，而另一种类型的栅极使用常规介电材料作为栅极电介质; 和（2）具有层叠铁电电容器和作为基本NAND存储器组串联电连接的场效应晶体管的FeRAM器件结构。 还提供了用于实现这种三维FeRAM器件的示例性制造工艺。