公开(公告)号：US09601604B2

公开(公告)日：2017-03-21

申请号：US14430585

申请日：2013-09-20

申请人： PST SENSORS (PROPRIETARY) LIMITED

发明人： David Thomas Britton ,  Margit Haerting ,  Stanley Douglas Walton

IPC分类号： H01L29/00 ,  H01L29/70 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L29/705 ,  H01C7/1013 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/72 ,  H01L49/02 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0504

摘要： An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

公开(公告)号：US20180130898A1

公开(公告)日：2018-05-10

申请号：US15604822

申请日：2017-05-25

申请人： Ideal Power, Inc.

发明人： Richard A. Blanchard ,  William C. Alexander

IPC分类号： H01L29/747 ,  H01L29/74 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/747 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66234 ,  H01L29/66295 ,  H01L29/66386 ,  H01L29/705 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7424

摘要： The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

公开(公告)号：US20120098096A1

公开(公告)日：2012-04-26

申请号：US12909632

申请日：2010-10-21

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 双极晶体管至少包括具有不同的第一和第二EB结深度的至少第一和第二连接的发射极 - 基极（EB）结，以及具有更大的第三深度的掩埋层（BL）集电极。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域覆盖第二EB结位置，从而提供其较浅的EB结深度。 BL收集器不是第一EB结的底部，并且与其横向间隔可变量以便于调节晶体管的性质。 在其他实施例中，BL收集器可以位于第二EB结的至少一部分的下面。 相反导电类型的区域过度叠加并且位于相对轻掺杂的BL集电极，从而保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US08791546B2

公开(公告)日：2014-07-29

申请号：US12909632

申请日：2010-10-21

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L29/73 ,  H01L29/735 ,  H01L29/70

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 双极晶体管至少包括具有不同的第一和第二EB结深度的至少第一和第二连接的发射极 - 基极（EB）结，以及具有更大的第三深度的掩埋层（BL）集电极。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域覆盖第二EB结位置，从而提供其较浅的EB结深度。 BL收集器不是第一EB结的底部，并且与其横向间隔可变量以便于调节晶体管的性质。 在其他实施例中，BL收集器可以位于第二EB结的至少一部分的下面。 相反导电类型的区域过度叠加并且位于相对轻掺杂的BL集电极，从而保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US3903542A

公开(公告)日：1975-09-02

申请号：US45027774

申请日：1974-03-11

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： NATHANSON HARVEY C ,  GREEN DAVID ,  DAVIS JR JOHN R

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L27/00 ,  H01L27/07 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/70 ,  H01L29/73 ,  H01L29/74 ,  H01L29/86 ,  H01L29/66

CPC分类号： H01L29/705 ,  H01L27/00 ,  H01L27/0705 ,  H01L29/00 ,  H01L29/0603 ,  H01L29/0684 ,  H01L29/40

摘要： A surface gate-induced semiconductor device is provided which exhibits conductivity modulated transient negative resistance. First and second base electrodes are spaced from each other and make ohmic contact to a semiconductor body adjacent a major surface thereof. An insulator layer with a gate electrode thereon is positioned on a major surface of the semiconductor body between the base electrodes. A gate bias voltage is applied to the gate electrode to form an inversion layer in the semiconductor body at the major surface adjacent the gate electrode. The modulation control signal is also applied to the gate electrode to inject minority carriers from the inversion layer into the semiconductor body and conductivity modulate an electric field applied across the body between the base electrodes by an interbase voltage source. The device is characterized by an operational parameter h 1 greater than 1 and preferably greater than 3. The semiconductor devices can be utilized in a spaced parallel array, preferably with common base electrodes, to form a neuristor device capable of propagating a minority carrier traveling wave without attenuation.

摘要翻译： 提供表面栅感应半导体器件，其表现出导电性调制的瞬态负电阻。 第一和第二基极彼此间隔开并与其主表面相邻的半导体本体欧姆接触。 其上具有栅电极的绝缘体层位于基极之间的半导体本体的主表面上。 栅极偏置电压施加到栅电极，在与栅电极相邻的主表面处在半导体本体中形成反型层。 调制控制信号也被施加到栅电极，以将少数载流子从反型层注入到半导体本体中，并通过基极间电压源对基极之间的电场进行导电调制。 该器件的特征在于大于1且优选大于3的操作参数h 1。半导体器件可以以间隔开的平行阵列（优选与公共基极）一起使用，以形成能够传播少数的神经元器件 载波行波无衰减。

公开(公告)号：US20190097031A1

公开(公告)日：2019-03-28

申请号：US15486921

申请日：2017-04-13

申请人： Ideal Power, Inc.

发明人： William C. Alexander ,  Richard A. Blanchard

IPC分类号： H01L29/747 ,  H01L29/06 ,  H01L29/40 ,  H03K17/66

CPC分类号： H01L29/747 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0642 ,  H01L29/1004 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42304 ,  H01L29/705 ,  H01L29/732 ,  H01L29/7325 ,  H03K17/66

摘要： Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

公开(公告)号：US20150236140A1

公开(公告)日：2015-08-20

申请号：US14430585

申请日：2013-09-20

申请人： PST SENSORS (PROPRIETARY) LIMITED

发明人： David Thomas Britton ,  Margit Haerting ,  Stanley Douglas Walton

IPC分类号： H01L29/70 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L29/705 ,  H01C7/1013 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/72 ,  H01L49/02 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0504

摘要： An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

摘要翻译： 公开了电子设备和制造电子设备的方法。 该装置包括半导体材料体和限定至少三个导电触点以形成相应端子的导电材料。 半导体材料和导电触头至少部分地重叠以限定器件，使得任何一对端子之间的器件的电特性对应于压敏电阻器的电特性。 半导体材料的主体可以是通过印刷或涂布沉积的层。 每对端子之间的变阻器特性使得能够以一种方式切换一个端子和任何两个其它端子之间的电流，使得当存在进入第一端子的正电流时，通过第二端子存在可忽略的电流， 施加正电位，并且相对于第二端子保持在负电位的第三端子中的正电流。 当第一端子有向外的负电流时，在第二端子中存在正电流，并且通过第三端子具有可忽略的电流。

公开(公告)号：US4182965A

公开(公告)日：1980-01-08

申请号：US825148

申请日：1977-08-16

申请人： Hans Pfleiderer

发明人： Hans Pfleiderer

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/70 ,  H01L29/735 ,  H01L29/82 ,  H01L29/86 ,  H01L29/861 ,  H01L29/868 ,  H01L43/08

CPC分类号： H01L29/70 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/12 ,  H01L29/705 ,  H01L29/735 ,  H01L29/82 ,  H01L29/868

摘要： A semiconductor device is disclosed in which an intrinsic or weakly doped semiconductor layer is arranged on a substrate. The semiconductor layer contains a first P doped zone and a first N doped zone which are separated by a portion of the said intrinsic layer serving as base zone. The semiconductor layer further contains a second P doped zone and a second N doped zone which are also separated from one another by the base zone. The four doped zones are arranged such that a connecting line between the second P doped zone and second N doped zone intersects a connecting line between the first P doped zone and the first N doped zone preferably at right angles. A sub-diode formed of the first doped zones affects the operation of a sub-diode formed by the second doped zones.

摘要翻译： 公开了一种半导体器件，其中本征或弱掺杂半导体层被布置在衬底上。 半导体层包含第一P掺杂区和第一N掺杂区，该第一P掺杂区和第一N掺杂区被作为基区的所述本征层的一部分分开。 半导体层还包含第二P掺杂区和第二N掺杂区，其也由基区彼此分离。 四个掺杂区被布置成使得第二P掺杂区和第二N掺杂区之间的连接线优选地以直角与第一P掺杂区和第一N掺杂区之间的连接线相交。 由第一掺杂区形成的子二极管影响由第二掺杂区形成的二极管的工作。

公开(公告)号：US09281375B2

公开(公告)日：2016-03-08

申请号：US14313114

申请日：2014-06-24

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L21/331 ,  H01L29/73 ,  H01L29/66 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/735 ,  H01L29/70

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 提供了制造双极晶体管的方法。 在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。 进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。 相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US20140308792A1

公开(公告)日：2014-10-16

申请号：US14313114

申请日：2014-06-24

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/735

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 提供了制造双极晶体管的方法。 在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。 进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。 相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。