公开(公告)号：US08908751B2

公开(公告)日：2014-12-09

申请号：US13036758

申请日：2011-02-28

申请人： Andrea Camuffo ,  Chi-Tao Goe ,  Bernhard Sogl ,  Sandro Pinarello ,  Jan-Erik Mueller ,  Nick Shute

发明人： Andrea Camuffo ,  Chi-Tao Goe ,  Bernhard Sogl ,  Sandro Pinarello ,  Jan-Erik Mueller ,  Nick Shute

IPC分类号： H04B3/46 ,  H03F3/21 ,  H03F1/32 ,  H03F1/02 ,  H03F3/72 ,  H03F1/24 ,  H04B1/04

CPC分类号： H04B1/0475 ,  H03F1/0255 ,  H03F1/0277 ,  H03F1/24 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/321 ,  H03F2201/3233 ,  H03F2203/7215 ,  H03F2203/7236 ,  H04B2001/0425

摘要： One embodiment of the present invention relates to a method and apparatus are provided herein for reducing the power consumption of a transmission chain while maintaining an acceptable figure of merit (e.g., linearity). In one embodiment, an adaptive biasing element is configured to perform adaptive biasing to reduce current consumption of a transmission chain by adjusting the operating point of one or more transmission chain elements (e.g., power amplifier, mixer, etc.). However, since adaptive biasing may reduce the linearity of a transmitted signal, its use is limited by the degradation of figure of merit caused by the introduced non-linearities. Accordingly, a pre-distortion element may be configured to perform adaptive digital pre-distortion (DPD) on a transmission chain input signal to account for non-linearities generated through the adaptive biasing, therefore allowing the adaptive biasing to further reduce the current consumption while maintaining an acceptable figure of merit.

摘要翻译： 本发明的一个实施例涉及一种方法和装置，用于在保持可接受的品质因数（例如线性度）的同时降低传输链的功率消耗。 在一个实施例中，自适应偏置元件被配置为执行自适应偏置以通过调整一个或多个传输链元件（例如，功率放大器，混频器等）的工作点来减小传输链的电流消耗。 然而，由于自适应偏置可以降低发射信号的线性度，所以其使用受到引入的非线性引起的品质因数的劣化的限制。 因此，预失真元件可以被配置为在传输链输入信号上执行自适应数字预失真（DPD），以解决通过自适应偏置产生的非线性，从而允许自适应偏置进一步降低电流消耗，同时 保持可接受的品质因数。

公开(公告)号：US20140348217A1

公开(公告)日：2014-11-27

申请号：US14280683

申请日：2014-05-19

申请人： MEDIATEK INC.

发明人： Ming-Yu Hsieh ,  Chi-Hsueh Wang ,  Pou-Chi Chang

IPC分类号： H04L27/34

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A transmitter system includes a digital phase rotator, a phase rotation controller, and a digital radio-frequency (RF) transmitter. The digital phase rotator receives a first constellation data, and applies a digital phase rotation to the received first constellation data to generate a second constellation data. The phase rotation controller configures the digital phase rotation. The digital RF transmitter receives a digital input data derived from the second constellation data, and converts the digital input data into an analog RF output.

摘要翻译： 发射机系统包括数字相位旋转器，相位旋转控制器和数字射频（RF）发射器。 数字相位旋转器接收第一星座数据，并且对所接收的第一星座数据应用数字相位旋转以产生第二星座数据。 相位旋转控制器配置数字相位旋转。 数字RF发射器接收从第二星座数据得到的数字输入数据，并将数字输入数据转换为模拟RF输出。

公开(公告)号：US09577638B2

公开(公告)日：2017-02-21

申请号：US14273547

申请日：2014-05-09

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

摘要翻译： 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US20160373243A1

公开(公告)日：2016-12-22

申请号：US15255159

申请日：2016-09-02

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

摘要翻译： 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US20140348269A1

公开(公告)日：2014-11-27

申请号：US14272522

申请日：2014-05-08

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chih-Jung Chen ,  Hsiang-Hui Chang

IPC分类号： H04W24/02 ,  H04B1/04

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.

摘要翻译： 数据转换装置包括：数据采样电路，被配置为对数字信号进行上采样以根据时钟信号产生上采样信号; 电压电平发生电路，被布置成产生可调电压; 以及信号转换电路，被配置为根据可调电压和上采样信号产生转换信号。

公开(公告)号：US20140348259A1

公开(公告)日：2014-11-27

申请号：US14271470

申请日：2014-05-07

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen

IPC分类号： H03M1/12 ,  H04B1/04

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.

摘要翻译： 信号转换装置包括：第一转换电路，被布置成接收第一输入信号; 以及耦合在所述第一转换电路的输出端子与参考电压之间的第一电容电路; 其中，所述第一转换电路被配置为根据所述第一输入信号在所述第一转换电路的输出端产生第一转换信号。

公开(公告)号：US09917586B2

公开(公告)日：2018-03-13

申请号：US15611822

申请日：2017-06-02

申请人： MediaTek Inc.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20 ,  H03F1/02 ,  H03F3/24

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US09698785B2

公开(公告)日：2017-07-04

申请号：US15255159

申请日：2016-09-02

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US20140348264A1

公开(公告)日：2014-11-27

申请号：US14281902

申请日：2014-05-20

申请人： MEDIATEK INC.

发明人： Wen-Chieh Wang ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  I-Wen Liu ,  Khurram Muhammad ,  Chih-Ming Hung

IPC分类号： H04B1/04 ,  H04L25/08 ,  H04L25/02

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

摘要翻译： 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。

公开(公告)号：US20140347127A1

公开(公告)日：2014-11-27

申请号：US14267929

申请日：2014-05-02

申请人： Mediatek Inc.

发明人： Yang-Chuan Chen ,  Hsiang-Hui Chang

IPC分类号： H03F3/217

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

摘要翻译： 开关功率放大器包括：由第一数字信号控制的第一晶体管，以选择性地输出第一输出信号; 由第二数字信号控制的第二晶体管，以选择性地输出第二输出信号; 以及控制电路，被配置为根据第一数字信号和第三数字信号产生第二数字信号; 其中所述第一输出信号和所述第二输出信号在所述第一晶体管和所述第二晶体管的公共连接的节点上输出。