公开(公告)号：US20130265108A1

公开(公告)日：2013-10-10

申请号：US13591061

申请日：2012-08-21

申请人： Joos Dieter ,  Wim Philibert ,  Patrick Reynaert ,  Dixian Zhao

发明人： Joos Dieter ,  Wim Philibert ,  Patrick Reynaert ,  Dixian Zhao

IPC分类号： H03F3/45

CPC分类号： H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/72 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/222 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/21106 ,  H03F2203/21142 ,  H03F2203/21175 ,  H03F2203/45018 ,  H03F2203/45036 ,  H03F2203/45172 ,  H03F2203/45206 ,  H03F2203/45556 ,  H03F2203/45566 ,  H03F2203/45592 ,  H03F2203/45621 ,  H03F2203/45638 ,  H03F2203/45726 ,  H03F2203/45728 ,  H03F2203/45731 ,  H03F2203/7221 ,  H03F2203/7224 ,  H03H7/48

摘要： An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.

摘要翻译： 具有功率组合器的极高频（EHF）双模PA采用40-nm大容量CMOS技术设计。 对于低功率应用，其中一个单元PA可以关闭。 在设计中，执行电路级优化和权衡，以确保两种模式的良好性能。 PA在高功率模式下实现了17.4dBm的PSAT和29.3％的PAE，在低功率模式下，PAAT为12.6dBm，PAE为19.6％。 还进行可靠性测量，并且基于常用的经验模型估计80613小时的寿命。 在该设计中实现的优异性能（例如，报告最高的PAE）进一步证实了CMOS技术的扩展将继续有利于mm波收发器设计。

公开(公告)号：US20120218043A1

公开(公告)日：2012-08-30

申请号：US13504710

申请日：2010-10-29

申请人： Robert Hwat Hian Teng

发明人： Robert Hwat Hian Teng

IPC分类号： H03F1/34 ,  H03F1/00

CPC分类号： H03F1/305 ,  H03F1/342 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/156 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/408 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/507 ,  H03F2200/522 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45151 ,  H03F2203/45171 ,  H03F2203/45206 ,  H03F2203/45226 ,  H03F2203/45528 ,  H03F2203/45536 ,  H03F2203/45586 ,  H03F2203/45588 ,  H03F2203/45618 ,  H03F2203/45728 ,  H03G3/34

摘要： An amplifier comprises a main amplification stage and an auxiliary amplification stage. An input of the main amplification stage and an input of the auxiliary amplification stage are coupled to a common node, and an output of the main amplification stage is coupled to an output node. During activation, before power is supplied to the main amplification stage, the output node is coupled to a reference voltage (VREF). A quiescent voltage is then established at the common node by coupling power to the auxiliary amplification stage. Only then is power coupled to the main amplification stage and the reference voltage (VREF) de-coupled from the output node.

摘要翻译： 放大器包括主放大级和辅助放大级。 主放大级的输入和辅助放大级的输入耦合到公共节点，并且主放大级的输出耦合到输出节点。 在激活期间，在向主放大级供电之前，输出节点耦合到参考电压（VREF）。 然后通过将功率耦合到辅助放大级，在公共节点建立静态电压。 只有此时功率耦合到主放大级和从输出节点去耦合的参考电压（VREF）。

公开(公告)号：US20190245497A1

公开(公告)日：2019-08-08

申请号：US15887816

申请日：2018-02-02

申请人： pSemi Corporation

发明人： Miles Sanner ,  Emre Ayranci

IPC分类号： H03F3/195 ,  H03F1/02

CPC分类号： H03F3/195 ,  H03F1/0211 ,  H03F1/223 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/249 ,  H03F2200/267 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/396 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2203/7209 ,  H04B1/16

摘要： A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

公开(公告)号：US20160173042A1

公开(公告)日：2016-06-16

申请号：US14839055

申请日：2015-08-28

申请人： Nvidia Corporation

发明人： Sherif Abdelhalem ,  Frank Zhang ,  Abdellatif Bellaouar ,  Sherif Embabi

IPC分类号： H03F3/193

CPC分类号： H03F3/193 ,  H03F1/0288 ,  H03F1/07 ,  H03F1/223 ,  H03F3/211 ,  H03F3/602 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/396 ,  H03F2200/429 ,  H03F2203/7209

摘要： A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

摘要翻译： 低噪声放大器包括耦合到输入信号的第一输入晶体管和耦合到输入信号的第二输入晶体管。 低噪声放大器还包括耦合在第一输入晶体管和第一载流子汇聚负载之间的第一输出晶体管，被配置为将第一输入晶体管连接到第一载流子聚集负载。 此外，低噪声放大器包括耦合在第一输入晶体管和第二载流子聚集负载之间的第二输出晶体管，被配置为将第一输入晶体管连接到第二载流子聚集负载。 此外，低噪声放大器包括耦合在第二输入晶体管和第二载流子聚集负载之间的第三输出晶体管，被配置为将第二输入晶体管连接到第二载流子聚集负载。 还包括操作低噪声放大器和扩展载波低噪声放大器的方法。

公开(公告)号：US09831838B2

公开(公告)日：2017-11-28

申请号：US14839055

申请日：2015-08-28

申请人： Nvidia Corporation

发明人： Sherif Abdelhalem ,  Frank Zhang ,  Abdellatif Bellaouar ,  Sherif Embabi

IPC分类号： H03F3/68 ,  H03F3/193 ,  H03F1/22 ,  H03F3/21 ,  H03F3/72 ,  H03F1/07 ,  H03F1/02 ,  H03F3/60

CPC分类号： H03F3/193 ,  H03F1/0288 ,  H03F1/07 ,  H03F1/223 ,  H03F3/211 ,  H03F3/602 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/396 ,  H03F2200/429 ,  H03F2203/7209

摘要： A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

公开(公告)号：US20170331366A1

公开(公告)日：2017-11-16

申请号：US15335956

申请日：2016-10-27

申请人： MediaTek Inc.

发明人： Ramy Awad

IPC分类号： H02M3/07

CPC分类号： H02M3/07 ,  H03F3/005 ,  H03F3/301 ,  H03F3/3069 ,  H03F3/505 ,  H03F2200/219 ,  H03F2200/231 ,  H03F2200/252 ,  H03F2200/27 ,  H03F2200/297 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/42 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513 ,  H03F2200/69

摘要： A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

公开(公告)号：US09722554B2

公开(公告)日：2017-08-01

申请号：US14845264

申请日：2015-09-03

申请人： LAPIS Semiconductor Co., Ltd.

发明人： Koji Higuchi

IPC分类号： H03F3/393 ,  H03F3/45 ,  G09G3/20

CPC分类号： H03F3/393 ,  G09G3/20 ,  G09G2310/0254 ,  G09G2310/0291 ,  G09G2320/0247 ,  G09G2330/026 ,  H03F3/45183 ,  H03F3/45775 ,  H03F2200/396 ,  H03F2200/417 ,  H03F2203/45212 ,  H03F2203/45586 ,  H03F2203/45588

摘要： When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal.

公开(公告)号：US08823449B2

公开(公告)日：2014-09-02

申请号：US13591061

申请日：2012-08-21

申请人： Joos Dieter ,  Wim Philibert ,  Patrick Reynaert ,  Dixian Zhao

发明人： Joos Dieter ,  Wim Philibert ,  Patrick Reynaert ,  Dixian Zhao

IPC分类号： H03F1/14

CPC分类号： H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/72 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/222 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/21106 ,  H03F2203/21142 ,  H03F2203/21175 ,  H03F2203/45018 ,  H03F2203/45036 ,  H03F2203/45172 ,  H03F2203/45206 ,  H03F2203/45556 ,  H03F2203/45566 ,  H03F2203/45592 ,  H03F2203/45621 ,  H03F2203/45638 ,  H03F2203/45726 ,  H03F2203/45728 ,  H03F2203/45731 ,  H03F2203/7221 ,  H03F2203/7224 ,  H03H7/48

摘要： An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.

摘要翻译： 具有功率组合器的极高频（EHF）双模PA采用40-nm大容量CMOS技术设计。 对于低功率应用，其中一个单元PA可以关闭。 在设计中，执行电路级优化和权衡，以确保两种模式的良好性能。 PA在高功率模式下实现了17.4dBm的PSAT和29.3％的PAE，在低功率模式下，PAAT为12.6dBm，PAE为19.6％。 还进行可靠性测量，并且基于常用的经验模型估计80613小时的寿命。 在该设计中实现的优异性能（例如，报告最高的PAE）进一步证实了CMOS技术的扩展将继续有利于mm波收发器设计。

公开(公告)号：US20190028075A1

公开(公告)日：2019-01-24

申请号：US16020047

申请日：2018-06-27

申请人： Sho KAMEZAWA ,  Tohru KANNO

发明人： Sho KAMEZAWA ,  Tohru KANNO

IPC分类号： H03F3/45 ,  H03F1/02

CPC分类号： H03F3/45188 ,  H03F1/0211 ,  H03F3/45089 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/129 ,  H03F2200/156 ,  H03F2200/297 ,  H03F2200/396 ,  H03F2203/45156 ,  H03F2203/45226 ,  H03F2203/45264 ,  H03F2203/45512 ,  H03F2203/45536

摘要： A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit. The feedback circuit is configured to feed the selected output back to the differential amplifier circuit.

公开(公告)号：US20180323821A1

公开(公告)日：2018-11-08

申请号：US15968927

申请日：2018-05-02

申请人： STMicroelectronics SA

发明人： Laurent CHABERT ,  Raphael PAULIN

IPC分类号： H04B1/48 ,  H04B1/16 ,  H04B1/18 ,  H03F3/195 ,  H03F1/26

CPC分类号： H04B1/48 ,  H03F1/26 ,  H03F1/523 ,  H03F3/195 ,  H03F3/72 ,  H03F2200/06 ,  H03F2200/114 ,  H03F2200/181 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/321 ,  H03F2200/396 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/507 ,  H03F2200/519 ,  H03F2200/525 ,  H03F2200/61 ,  H03F2200/75 ,  H04B1/1615 ,  H04B1/18

摘要： A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.