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公开(公告)号：US20240235504A9
公开(公告)日：2024-07-11
申请号：US17972518
申请日：2022-10-24
Applicant: Texas Instruments Incorporated
Inventor： Harsh Sheokand , Tarunvir Singh , Anant Kamath , Suvadip Banerjee
IPC: H03F3/45
CPC classification number: H03F3/45654 , H03F3/45183 , H03F2203/45526
Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.
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公开(公告)号：US20230283244A1
公开(公告)日：2023-09-07
申请号：US17683825
申请日：2022-03-01
Inventor： Gregory S. Notaro , James M. Bock
CPC classification number: H03F1/42 , H03F3/45475 , H03F2200/36 , H03F2203/45526
Abstract: A transimpedance amplifier system (TIA) for stabilizing high gain and high frequency signals while minimizing parasitic capacitance effects on the transimpedance amplifier system. The TIA includes an operational amplifier having a first input terminal, a second input terminal, and an output terminal. The TIA also includes a signal generating device operatively connected with the first input terminal of the operational amplifier. The TIA also includes a T-network feedback architecture operatively connected with the operational amplifier at the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The T-network feedback architecture has a first impedance network and a second impedance network. The T-network feedback architecture is configured to suppress parasitic capacitance from the transimpedance amplifier system.
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公开(公告)号：US11716061B2
公开(公告)日：2023-08-01
申请号：US17665399
申请日：2022-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Modaffari , Germano Nicollini
CPC classification number: H03F3/45273 , H03F3/45269 , H03F2203/45526
Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
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4.发明申请
公开(公告)号：US20190229689A1
公开(公告)日：2019-07-25
申请号：US16372164
申请日：2019-04-01
Applicant: Luxtera, Inc.
Inventor： Brian Welch
CPC classification number: H03F3/45237 , G01J1/44 , H03F1/34 , H03F3/087 , H03F3/45071 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/405 , H03F2203/45222 , H03F2203/45288 , H03F2203/45511 , H03F2203/45526
Abstract: A system for a differential trans-impedance amplifier circuit comprising: an amplifier having a pair of input nodes and configured to generate an amplified replica of a differential voltage on said pair of input nodes; a photodiode; a pair of capacitors coupling said photodiode to said pair of input nodes; at least one resistance coupled between said pair of input nodes of said amplifier; and a bias network comprising two photodiode biasing resistances each photodiode biasing resistance coupled in series between said photodiode and a respective DC voltage. A feedback loop for the amplifier may include source followers that are operable to level shift voltages prior to coupling capacitors that couple said photodiode to said amplifier to ensure stable bias conditions for said amplifier. The source followers may include CMOS transistors. The amplifier may be integrated in a complementary metal-oxide semiconductor (CMOS) chip, which may include a CMOS photonics chip.
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公开(公告)号：US20190109571A1
公开(公告)日：2019-04-11
申请号：US16152505
申请日：2018-10-05
Applicant: THINE ELECTRONICS, INC.
Inventor： Yuji GENDAI
CPC classification number: H03G1/0088 , H03F3/45273 , H03F3/45475 , H03F2203/45526 , H03F2203/45528 , H03G1/0029 , H03G1/007 , H03G3/001
Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.
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公开(公告)号：US10056915B2
公开(公告)日：2018-08-21
申请号：US14937175
申请日：2015-11-10
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Akinobu Onishi
IPC: H04B15/00 , H03M1/66 , H03M1/00 , H03M3/00 , H03M1/70 , H03M1/06 , H04R3/00 , H03F3/45 , H03F3/187
CPC classification number: H03M1/661 , H03F3/187 , H03F3/45475 , H03F2200/03 , H03F2203/45526 , H03M1/002 , H03M1/0626 , H03M1/70 , H03M3/32 , H03M3/344 , H03M3/502 , H03M3/508 , H03M3/51 , H04R3/00
Abstract: A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital signal and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital signal and upon the received clock, wherein the first and second DACs are connected in parallel and process the same multi-bit digital signal. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier is connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.
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公开(公告)号：US20180191312A1
公开(公告)日：2018-07-05
申请号：US15316562
申请日：2016-05-02
Applicant: Telefonaktiebolaget LM Ericsson (publ)
Inventor： Fenghao MU
CPC classification number: H03F1/342 , H03F3/195 , H03F3/45179 , H03F2200/144 , H03F2200/21 , H03F2200/222 , H03F2200/294 , H03F2200/451 , H03F2200/546 , H03F2203/45024 , H03F2203/45236 , H03F2203/45241 , H03F2203/45512 , H03F2203/45524 , H03F2203/45526 , H04B1/0053 , H04B1/0082 , H04B1/1638 , H04B1/18
Abstract: An amplifier for a receiver circuit is disclosed. The amplifier has an input node (Vin) and an output node (Vout). It comprises a tunable tank circuit connected to the output node (Vout), a feedback circuit path connected between the output node (Vout) and the input node (Vin), and a tunable capacitor connected between an internal node of the feedback circuit path and a reference-voltage node. A receiver circuit and a communication apparatus is disclosed as well.
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公开(公告)号：US09993386B2
公开(公告)日：2018-06-12
申请号：US14556077
申请日：2014-11-28
Applicant: Louis G. Racette
Inventor： Louis G. Racette
CPC classification number: A61H23/00 , A61H19/00 , A61H23/02 , A61H2201/165 , A61H2201/5015 , A61H2201/5043 , A61H2201/5097 , A61H2230/105 , H03F3/211 , H03F3/45475 , H03F2200/261 , H03F2200/411 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45548 , H03F2203/45571 , H03F2203/45572 , H03F2203/45594 , H03F2203/45654
Abstract: An instrumentation absolute value differential amplifier is used as part of an electroencephalogram, electromyogram or electrocardiogram to quantify the excitation state of a user, processing and transmitting this information as a control signal for a user feedback device. In one possible arrangement, this feedback device includes a wireless sex toy which responds to the sent control information, acting as a mind controlled sex toy. This provides a simple, intuitive, aesthetically appealing interface for creating a unique sexual experience. The use of an instrumentation absolute value differential amplifier is sufficient to monitor the desired signals while reducing the number of parts required and allowing for less precise tolerances than traditional biological monitoring circuits, thus decreasing the cost of production.
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公开(公告)号：US09966908B1
公开(公告)日：2018-05-08
申请号：US15612826
申请日：2017-06-02
Applicant: Xilinx, Inc.
Inventor： Declan Carey
CPC classification number: H03F1/52 , H03F3/195 , H03F3/45475 , H03F3/45937 , H03F3/45973 , H03F2200/111 , H03F2200/441 , H03F2200/444 , H03F2200/451 , H03F2203/45101 , H03F2203/45134 , H03F2203/45138 , H03F2203/45512 , H03F2203/45526 , H03F2203/45586 , H03F2203/45678 , H03H11/0422 , H03K19/018528 , H04B1/16 , H04L25/03
Abstract: A circuit for implementing a differential input receiver is described. The circuit comprises an input circuit having a first input node and a second input node configured to receive a differential input signal; a first output circuit having a first capacitor coupled between the first input node and a first output node and a second capacitor coupled between the second input node and a second output node, wherein the first output circuit generates an output signal at the first output and the second output when the input signal is in a first frequency range; and a second output circuit comprising an amplifier having a first amplifier input coupled to the first input node and a second amplifier input coupled to the second input node, wherein the second output circuit generates an output signal when the input signal is in a second frequency range which extends lower than the first frequency range. A method of implementing a differential input receiver is also described. The circuits and methods also allow for offset compensation.
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公开(公告)号：US09755680B2
公开(公告)日：2017-09-05
申请号：US15276308
申请日：2016-09-26
Applicant: Jianxun Zhu , Peter R. Kinget
Inventor： Jianxun Zhu , Peter R. Kinget
CPC classification number: H04B1/1638 , H03F3/19 , H03F3/195 , H03F3/265 , H03F3/45179 , H03F3/45192 , H03F3/45475 , H03F2200/294 , H03F2200/336 , H03F2200/451 , H03F2203/45288 , H03F2203/45512 , H03F2203/45526
Abstract: Circuits for field-programmable receiver front ends are provided. These front ends can include a field programmable common source low noise transconductance amplifier (LNTA), a field programmable common gate LNTA, first and second four-phase I/Q mixers, first, second, third, and fourth transimpedance amplifiers, an I-path complex combiner, and a Q-path complex combiner. Transconductance cells in each of the field programmable common source LNTA and field programmable common gate LNTA can be programmed to operate in one of a class-AB mode, a class-C mode, and an OFF mode.
