公开(公告)号：US20040078771A1

公开(公告)日：2004-04-22

申请号：US10630762

申请日：2003-07-31

发明人： David A. Sobel

IPC分类号： G06F017/50

CPC分类号： H03F3/45739 ,  H03F3/45192 ,  H03F3/4539 ,  H03F3/45475 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726 ,  H03G1/0088

摘要： Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

摘要翻译： 提供了一种降低构造并布置在集成电路（IC）衬底上的电路中的阻抗变化的方法。 该方法包括形成一组并联的电阻器，每一组对应于IC上的一个阻抗器件。 每组还包括两个或多个并联电阻器路径，每个电阻器路径包括两个或多个级联电阻器，并且具有基本上等于其对应的阻抗器件的预定阻抗值的总阻抗值。 最后，该方法包括在电路放置在IC上时，配置并联电阻器路径集合以跨越衬底形成叉指结构。

公开(公告)号：US20040000955A1

公开(公告)日：2004-01-01

申请号：US10184148

申请日：2002-06-27

发明人： Yueyong Wang ,  Chanh Tran

IPC分类号： H03F003/45

CPC分类号： H03F3/45739 ,  H03F3/45188 ,  H03F2203/45642 ,  H03F2203/45686

摘要： A circuit, apparatus and method for providing a balanced differential signal from incoming serial data having high or low voltage swings are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a voltage source and a current source coupled to a node. A first electrical path is coupled to the voltage source and the node. A second electrical path is coupled to the voltage source and the node. The first path includes a first transistor having a first gate and a first channel. The first transistor gate is adapted to receive a reference voltage. The second path includes a second transistor having a second gate and a second channel. The second transistor gate is adapted to receive a data voltage that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path, and provides a predetermined resistance responsive to a control signal. A signal processing circuit is coupled to the variable resistor and the node. The signal processing circuit generates a control signal responsive to the node voltage.

公开(公告)号：US20020060598A1

公开(公告)日：2002-05-23

申请号：US09940472

申请日：2001-08-29

申请人： NEC CORPORATION

发明人： Katsuji Kimura

IPC分类号： G06G007/14

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

摘要翻译： 电压减法器/加法器电路包括具有第一和第二MOS晶体管的差分对。 第一和第二MOS晶体管的栅电极形成用于接收输入差分电压的输入端。 第一和第二MOS晶体管的漏极形成用于输出减法输出信号的输出端。 第一和第二MOS晶体管的源电极共同耦合以形成用于加法输出电压的输出端。 流过第一和第二MOS晶体管的电流的总和与输入差分电压的平方成比例地增加。 也可以通过恒定电流源来驱动差分对。 可以提供电平移位器用于对来自共同耦合的源电极的相加输出电压进行电平移位。

公开(公告)号：US07061318B2

公开(公告)日：2006-06-13

申请号：US11103424

申请日：2005-04-12

申请人： David A. Sobel

发明人： David A. Sobel

IPC分类号： H03F3/45

CPC分类号： H03F3/45739 ,  H03F3/45192 ,  H03F3/4539 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726 ,  H03G1/0088

摘要： A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

公开(公告)号：US07026875B2

公开(公告)日：2006-04-11

申请号：US10944007

申请日：2004-09-20

申请人： David A. Sobel

发明人： David A. Sobel

IPC分类号： H03G3/30

CPC分类号： H03G1/0088 ,  H03F3/45192 ,  H03F3/4539 ,  H03F3/45739 ,  H03F3/45995 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726

摘要： Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

公开(公告)号：US20030140320A1

公开(公告)日：2003-07-24

申请号：US10208043

申请日：2002-07-31

申请人： Broadcom Corporation

发明人： David A. Sobel

IPC分类号： G06F017/50

CPC分类号： H03F3/45739 ,  H03F3/45192 ,  H03F3/4539 ,  H03F3/45475 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726 ,  H03G1/0088

摘要： Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

摘要翻译： 提供了一种降低构造并布置在集成电路（IC）衬底上的电路中的阻抗变化的方法。 该方法包括形成一组并联的电阻器，每一组对应于IC上的一个阻抗器件。 每组还包括两个或多个并联电阻器路径，每个电阻器路径包括两个或多个级联电阻器，并且具有基本上等于其对应的阻抗器件的预定阻抗值的总阻抗值。 最后，该方法包括在电路放置在IC上时，配置并联电阻器路径集合以跨越衬底形成叉指结构。

公开(公告)号：US20030137349A1

公开(公告)日：2003-07-24

申请号：US10338918

申请日：2003-01-09

申请人： Broadcom Corporation

发明人： David A. Sobel

IPC分类号： H03F003/45

CPC分类号： H03F3/45739 ,  H03F3/45192 ,  H03F3/4539 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726 ,  H03G1/0088

摘要： A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

公开(公告)号：US20030052731A1

公开(公告)日：2003-03-20

申请号：US10234129

申请日：2002-09-05

申请人： NEC CORPORATION

发明人： Katsuji Kimura

IPC分类号： G06G007/12

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

公开(公告)号：US5283535A

公开(公告)日：1994-02-01

申请号：US937313

申请日：1992-09-01

申请人： Joannes M. J. Sevenhans ,  Mark G. S. J. Van Paemel

发明人： Joannes M. J. Sevenhans ,  Mark G. S. J. Van Paemel

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45179 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/4569 ,  H03F3/45739 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45078 ,  H03F2203/45466 ,  H03F2203/45612 ,  H03F2203/45641 ,  H03F2203/45648

摘要： An arrangement includes a differential amplifier pair configured as first and second amplifier branches with first and second input terminals respectively. The first and second amplifier branches are connected at a junction point to a common branch which includes a current source. A control circuit regulates the current of the current source to linearize an input/output characteristic of the amplifier differential pair. The control circuit includes a negative feedback circuit having a comparator, a first input of the comparator being connected to a reference voltage terminal to which an external reference voltage is applied, a second input of the comparator being connected to the amplifier branch junction point and an output of the comparator connected for controlling the current source.

摘要翻译： 一种布置包括分别配置有第一和第二输入端的第一和第二放大器的差分放大器对。 第一和第二放大器分支在连接点处连接到包括电流源的公共分支。 控制电路调节电流源的电流以使放大器差分对的输入/输出特性线性化。 所述控制电路包括具有比较器的负反馈电路，所述比较器的第一输入端连接到施加了外部参考电压的基准电压端子，所述比较器的第二输入端连接到所述放大器支路连接点， 用于控制电流源的比较器的输出。

公开(公告)号：USRE43776E1

公开(公告)日：2012-10-30

申请号：US12346521

申请日：2008-12-30

申请人： David A. Sobel

发明人： David A. Sobel

IPC分类号： H03G3/12 ,  H01L25/00 ,  G06F17/50

CPC分类号： H03F3/45739 ,  H03F3/45192 ,  H03F3/4539 ,  H03F3/45475 ,  H03F2203/45521 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03F2203/45698 ,  H03F2203/45726 ,  H03G1/0088

摘要： Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

摘要翻译： 提供了一种降低构造并布置在集成电路（IC）衬底上的电路中的阻抗变化的方法。 该方法包括形成一组并联的电阻器，每一组对应于IC上的一个阻抗器件。 每组还包括两个或多个并联电阻器路径，每个电阻器路径包括两个或多个级联电阻器，并且具有基本上等于其对应的阻抗器件的预定阻抗值的总阻抗值。 最后，该方法包括在电路放置在IC上时，配置并联电阻器路径集合以跨越衬底形成叉指结构。