利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.016 秒)

    Digital logic protocol interface for different semiconductor technologies
    1.
    发明授权
    Digital logic protocol interface for different semiconductor technologies 失效
    用于不同半导体技术的数字逻辑协议接口

    公开(公告)号：US5298808A

    公开(公告)日：1994-03-29

    申请号：US825109

    申请日：1992-01-23

    申请人： William C. Terrell ,  Robert N. Deming ,  Russell S. Hinds

    发明人： William C. Terrell ,  Robert N. Deming ,  Russell S. Hinds

    IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/00361 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535 ,  H03K19/09429

    摘要： A method and apparatus for implementing silicon logic interface protocols in compound semiconductor technology converts the voltages corresponding to standard logic digital values to voltages appropriate to these digital values in compound semiconductor technology, and vice versa. In an input buffer circuit of the present invention, the voltage of the converted logic level depends only on the difference between the input standard voltage level and a reference voltage which corresponds to the threshold voltage of silicon logic so that the converted voltage is independent of device process, circuit temperature, and power supply output variations to first order. A source follower input is used so that the driving logic circuit need not source current to or sink current from the input buffer circuit so that fanout is not limited. An output buffer circuit of the present invention achieves a stable output buffer tri-state functionality and eliminates leakage current problems by a modification of a standard totem pole output configuration. A standard totem pole type output is modified to use a second pull-down MESFET which puts the source of the first pull-down MESFET at a small positive voltage. As a result, the gate-source diode of the first pull-down MESFET is reverse biased, shutting the first pull-down MESFET off hard.

    摘要翻译： 用于在化合物半导体技术中实现硅逻辑接口协议的方法和装置将对应于标准逻辑数字值的电压转换成适合于化合物半导体技术中的这些数字值的电压，反之亦然。 在本发明的输入缓冲器电路中，转换的逻辑电平的电压仅取决于输入标准电压电平与对应于硅逻辑的阈值电压的参考电压之间的差异，使得转换的电压与器件无关 过程，电路温度和电源输出变化到一级。 使用源极跟随器输入，使得驱动逻辑电路不需要从输入缓冲器电路来源电流或吸收电流，使得扇出不受限制。 本发明的输出缓冲电路通过修改标准图腾柱输出配置实现了稳定的输出缓冲器三态功能并消除漏电流问题。 修改了标准图腾柱输出以使用将第一下拉MESFET的源极放置在小正电压的第二下拉MESFET。 结果，第一个下拉MESFET的栅极 - 源极二极管被反向偏置，关闭了第一个下拉MESFET。

    Interface circuit between two circuits of different logic types
    2.
    发明授权
    Interface circuit between two circuits of different logic types 失效
    不同逻辑类型的两个电路之间的接口电路

    公开(公告)号：US5045727A

    公开(公告)日：1991-09-03

    申请号：US538703

    申请日：1990-06-15

    申请人： Jean-Yves Danckaert ,  Ernesto Perea

    发明人： Jean-Yves Danckaert ,  Ernesto Perea

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018535

    摘要： This interface constitutes an adaptation of the output signals of a first circuit, made of silicon for example, to the limit values of the input signals in a second digital circuit, made of GaAs for example. It includes a first stage (A) consisting of two parallel-mounted shifters, in which the input signal (E) and a reference (Ref) are shifted. A second stage (B), of the BFL type, compares these two values and a third stage (C) regenerates and amplifies the signals. A fourth stage (D) may give a complementary value. This interface is integrated into the chip of the second digital circuit which is made of GaAs.

    摘要翻译： 该接口构成例如由例如由硅制成的第一电路的输出信号到例如由GaAs制成的第二数字电路中的输入信号的极限值。 它包括由两个并联安装的移位器组成的第一级（A），其中输入信号（E）和参考（Ref）被移位。 BFL型的第二级（B）比较这两个值，第三级（C）再生并放大信号。 第四阶段（D）可以给出补充价值。 该接口集成在由GaAs制成的第二数字电路的芯片中。

    Translator circuit for converting ECL type signals to TTL type signals
    3.
    发明授权
    Translator circuit for converting ECL type signals to TTL type signals 失效
    用于将ECL型信号转换为TTL型信号的转换器电路

    公开(公告)号：US5030854A

    公开(公告)日：1991-07-09

    申请号：US505852

    申请日：1990-04-05

    申请人： Mark E. Fitzpatrick ,  Raymond E. Bloker

    发明人： Mark E. Fitzpatrick ,  Raymond E. Bloker

    IPC分类号： H03K19/018 ,  H03K19/0185 ,  H03K19/0952

    CPC分类号： H03K19/0952 ,  H03K19/018535

    摘要： The present electrical circuit functions to couple together circuits which may have different signal operating levels, such as circuits having small-swing ECL operating levels and large-swing TTL operating levels. The present circuit outputs a signal which is virtually unaffected by any non-ideal characteristics of transistors comprising the circuit.

    摘要翻译： 本电路用于将可能具有不同信号操作电平的电路耦合在一起，例如具有小摆幅ECL操作电平的电路和大摆幅TTL操作电平。 本电路输出几乎不受包括电路的晶体管的任何非理想特性影响的信号。

    Buffer circuit having Schottky gate transistors adjusting amplitude of output signal
    7.
    发明授权
    Buffer circuit having Schottky gate transistors adjusting amplitude of output signal 有权
    具有肖特基门晶体管的缓冲电路，其调节输出信号的幅度

    公开(公告)号：US06366142B1

    公开(公告)日：2002-04-02

    申请号：US09694326

    申请日：2000-10-24

    申请人： Hiroyuki Yamada

    发明人： Hiroyuki Yamada

    IPC分类号： H03B100

    CPC分类号： H03K19/018535

    摘要： A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.

    摘要翻译： 具有输入和输出端的缓冲电路包括连接在电压设定节点和地之间的第一肖特基晶体管晶体管，连接在电源和电压设定节点之间的负载装置，连接在输出端和地之间的第二肖特基晶体管 所述第二肖特基栅极晶体管的栅极连接到所述电压设定节点，连接在所述输出端子与所述电源之间的第三肖特基栅极晶体管，所述第三肖特基栅极晶体管的栅极连接到所述输入端子，电阻器装置 连接第一肖特基栅极晶体管的栅极和输入端，用于增加施加到第三肖特基栅极晶体管的栅极的电压电平。

    FETs logic circuit
    8.
    发明授权
    FETs logic circuit 失效
    FET逻辑电路

    公开(公告)号：US5909128A

    公开(公告)日：1999-06-01

    申请号：US823039

    申请日：1997-03-21

    申请人： Tadashi Maeda

    发明人： Tadashi Maeda

    IPC分类号： H01L21/8238 ,  G05F3/24 ,  H01L27/092 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0952 ,  H03K19/094

    CPC分类号： H03K19/018535 ,  G05F3/247 ,  H03K19/0952

    摘要： A semiconductor integrated circuit having a field effect transistor formed on a compound semiconductor is disclosed, that comprises a first power supply, a second power supply for supplying a voltage lower than a voltage that the first power supplies, and at least one virtual power supply that is not connected to the outside and that has a voltage between the voltage of the first power supply and the voltage of the second power supply, wherein the number of the virtual power supplies is designated to a value larger than the quotient of which the voltage between the first power supply and the second power supply is divided by the forward turn-on voltage of a gate electrode of the field effect transistor. In the case that a signal received from a circuit with a low voltage is connected to a circuit between any power supply, the signal is received by a directly coupled logic circuit with a depletion type field effect transistor as a drive circuit. The threshold voltage of the depletion type field effect transistor is -.DELTA.V or higher where .DELTA.V is the voltage between each power supply.

    摘要翻译： 公开了一种具有形成在化合物半导体上的场效应晶体管的半导体集成电路，其包括第一电源，用于提供低于第一电源供应的电压的第二电源，以及至少一个虚拟电源， 没有连接到外部，并且具有第一电源的电压和第二电源的电压之间的电压，其中虚拟电源的数量被指定为大于虚拟电源的数量的值， 第一电源和第二电源被场效应晶体管的栅极的正向导通电压除。 在从具有低电压的电路接收的信号连接到任何电源之间的电路的情况下，该信号由具有耗尽型场效应晶体管的直接耦合逻辑电路作为驱动电路接收。 耗尽型场效应晶体管的阈值电压为△DELTA V或更高，其中DELTA V为每个电源之间的电压。

    Interface circuit adapted for connection to following circuit using metal-semiconductor type transistor
    9.
    发明授权
    Interface circuit adapted for connection to following circuit using metal-semiconductor type transistor 失效
    接口电路适用于使用金属半导体型晶体管连接到后续电路

    公开(公告)号：US5592108A

    公开(公告)日：1997-01-07

    申请号：US506638

    申请日：1995-07-25

    申请人： Kazuhisa Tsukahara

    发明人： Kazuhisa Tsukahara

    IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/0952

    CPC分类号： H03K19/018535

    摘要： An interface circuit includes an input current limiting circuit for limiting a current of an input signal fed from a preceding circuit, thereby outputting the current-limited signal to a following circuit which is constituted using a MES type transistor. The interface circuit also includes a level shifting circuit supplied with a first higher power supply voltage and a lower power supply voltage, for converting a level of the current-limited signal into a logic level of the following circuit which is supplied with a second higher power supply voltage. The interface circuit further includes a level judging circuit connected between the input current limiting circuit and the level shifting circuit, for judging a logic threshold level of the input signal based on a predetermined level reference voltage. By the constitution, it is possible to adapt the interface circuit for connection to the following circuit constituted using MES type transistors.

    摘要翻译： 接口电路包括用于限制从先前电路馈送的输入信号的电流的输入限流电路，从而将电流限制信号输出到使用MES型晶体管构成的跟随电路。 接口电路还包括提供有第一较高电源电压和较低电源电压的电平移位电路，用于将限流信号的电平转换成提供有第二较高功率的后续电路的逻辑电平 电源电压。 接口电路还包括连接在输入限流电路和电平移动电路之间的电平判断电路，用于基于预定电平参考电压来判断输入信号的逻辑门限电平。 通过该结构，可以使用MES型晶体管构成的后续电路来连接接口电路。

    GaAs driver circuit
    10.
    发明授权
    GaAs driver circuit 失效
    GaAs驱动电路

    公开(公告)号：US5293085A

    公开(公告)日：1994-03-08

    申请号：US728546

    申请日：1985-04-29

    申请人： John J. Ennis ,  Gary L. Heimbigner

    发明人： John J. Ennis ,  Gary L. Heimbigner

    IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03K19/017 ,  H03K19/0175

    CPC分类号： H03K19/018535

    摘要： The invention comprises a gallium arsenide driver with float capability for logic high and logic low signals including logic means for receiving an input signal and providing logic high and low signals therefrom. Level shift means responsive to the high and low signals downshift the voltage levels thereof. Common gate means responsive to the downshifted signal voltage levels amplify these signals, and output source-follower means responsive to the amplified signals provide output signals to a pad.

    摘要翻译： 本发明包括具有用于逻辑高和逻辑低信号的浮动能力的砷化镓驱动器，包括用于接收输入信号并从其提供逻辑高和低信号的逻辑装置。 电平移位装置响应于高电平和低电平信号降低其电压电平。 响应于降档的信号电压电平的公共门装置放大这些信号，并且响应于放大的信号的输出源跟随器装置向衬垫提供输出信号。