公开(公告)号：US07656234B2

公开(公告)日：2010-02-02

申请号：US11874926

申请日：2007-10-19

申请人： Hiroyuki Satoh

发明人： Hiroyuki Satoh

IPC分类号： H03L7/085

CPC分类号： H03K19/0866 ,  H03K3/289 ,  H03K23/667

摘要： A circuit includes a logic circuit containing a first transistor and a second transistor which are connected in series to each other between a high power supply and a low power supply in such a manner that an emitter of one of the first and second transistors is connected to a collector of the other of the first and second transistors. The first transistor is positioned closer to the high power supply, and the second transistor is positioned closer to the low power supply. The logic circuit operates in accordance with voltages input into bases of the first and second transistors. The circuit further includes a current amplifying circuit containing a third transistor whose collector is connected to one of the high and low power supplies, whose emitter is connected to the other of the high and low power supplies, and whose base is connected to an output from the logic circuit. The current amplifying circuit amplifies a current of a logic signal from the logic circuit and feeds, from the emitter of the third transistor, the current-amplified logic signal back to the base of the second transistor.

摘要翻译： 电路包括逻辑电路，该逻辑电路包含第一晶体管和第二晶体管，这些第一晶体管和第二晶体管以这样的方式彼此串联连接，即第一和第二晶体管之一的发射极连接到 第一和第二晶体管中的另一个的集电极。 第一晶体管位于更靠近高电源的位置，第二晶体管位于更靠近低电源的位置。 逻辑电路根据输入到第一和第二晶体管的基极的电压进行工作。 该电路还包括一个电流放大电路，该电流放大电路包含第三晶体管，其集电极连接到高电源和低电源之一，其发射极连接到高电源和低电源中的另一个，其基极连接到 逻辑电路。 电流放大电路从逻辑电路放大逻辑信号的电流，并从第三晶体管的发射极将电流放大的逻辑信号反馈回第二晶体管的基极。

公开(公告)号：US5034630A

公开(公告)日：1991-07-23

申请号：US476539

申请日：1990-02-07

申请人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

发明人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

IPC分类号： H03K19/086 ,  H03M7/00 ,  H03M7/14 ,  H03M7/16

CPC分类号： H03M7/14 ,  H03K19/0866 ,  H03M7/165

摘要： A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

公开(公告)号：US4719629A

公开(公告)日：1988-01-12

申请号：US792097

申请日：1985-10-28

申请人： Wen-Yuan Wang

发明人： Wen-Yuan Wang

IPC分类号： G06F11/18 ,  H03K19/003 ,  H03K19/086 ,  H03K19/173

CPC分类号： H03K19/0866 ,  H03K19/00392 ,  H03K19/086 ,  H03K19/1738

摘要： An error correcting logic circuit for masking faults on dual redundant interconnections. Both interconnections are inmput to a NAND or AND circuit which includes pull-up resistors to a high potential. The outputs of all the NAND circuits are connected to dual redundant logic circuits, each of which has an emitter-follower output with a load resistor to ground. The outputs of the redundant logic circuits provide the redundant interconnections to other similar error correcting logic circuits.

摘要翻译： 用于屏蔽双冗余互连故障的纠错逻辑电路。 这两个互连都是对包括上拉电阻到高电位的NAND或AND电路的输入。 所有NAND电路的输出连接到双冗余逻辑电路，每个冗余逻辑电路具有发射极跟随器输出，并具有负载电阻到地。 冗余逻辑电路的输出为其他类似的纠错逻辑电路提供冗余互连。

公开(公告)号：US4585957A

公开(公告)日：1986-04-29

申请号：US488333

申请日：1983-04-25

申请人： William J. Ooms

发明人： William J. Ooms

IPC分类号： H03K3/2885 ,  H03K3/289 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/0866 ,  H03K19/013 ,  H03K19/086 ,  H03K3/2885 ,  H03K3/289

摘要： Diode load emitter coupled logic circuits is described that utilizes forward biased diodes in the load circuits. The load circuits may be comprised of a single diode or two or more diodes connected in series. If a single diode is used in the load circuits, the slope factor of the diode must be greater than or equal to the slope factor of switching transistors in the logic circuit. External bias circuitry provides a bias current which can be varied for varying the frequency of operation of the logic circuit. High speeds at low power dissipations can be obtained since the switching transistors in the logic circuits do not switch completely on and off.

摘要翻译： 描述了在负载电路中利用正向偏置二极管的二极管负载发射极耦合逻辑电路。 负载电路可以由串联连接的单个二极管或两个或更多个二极管组成。 如果在负载电路中使用单个二极管，二极管的斜率必须大于或等于逻辑电路中开关晶体管的斜率因子。 外部偏置电路提供可以改变逻辑电路的操作频率的偏置电流。 由于逻辑电路中的开关晶体管不能完全导通和截止，所以可以获得低功耗的高速度。

公开(公告)号：US4408134A

公开(公告)日：1983-10-04

申请号：US226323

申请日：1981-01-19

申请人： Michael Allen

发明人： Michael Allen

IPC分类号： H03K19/086 ,  H03K19/21 ,  H03K19/20

CPC分类号： H03K19/212 ,  H03K19/0866

摘要： A unitary logic circuit for performing the function of an EXCLUSIVE OR logic gate, the output terminal of which forms a first input terminal to an AND logic gate. Implemented in emitter-coupled logic technology, the circuit has a fast response time with low power consumption.

摘要翻译： 用于执行EXCLUSIVE OR逻辑门的功能的单一逻辑电路，其输出端形成与逻辑门的第一输入端。 采用发射极耦合逻辑技术实现，电路响应时间快，功耗低。

公开(公告)号：US3686512A

公开(公告)日：1972-08-22

申请号：US3686512D

申请日：1970-07-07

申请人： SIEMENS AG

发明人： KROOS FRIEDRICH-KARL

IPC分类号： G06F7/50 ,  G06F7/501 ,  H03K19/086 ,  H03K19/22

CPC分类号： G06F7/501 ,  G06F2207/4806 ,  H03K19/0866

摘要： A logic circuit to reduce the transit time of a signal and to make the circuit more easily subject to integration as a single element. The logic circuit includes two logic partial circuits, each having two current switches. The partial circuits are coupled to the bases of two emitter follower transistors with the emitters of the two transistors coupled to a joint gate resistance and to an outlet clamp. The first partial circuit forms an AND linkage and the coupling of the two partial circuits of an additional transistor which is connected in parallel with one of the current switches of the second partial circuit forms an OR gate.

摘要翻译： 一种用于减少信号传播时间并使电路更容易集成为单一元件的逻辑电路。 逻辑电路包括两个逻辑部分电路，每个具有两个电流开关。 部分电路耦合到两个射极跟随器晶体管的基极，两个晶体管的发射极耦合到接合栅极电阻和出口钳位。 第一部分电路形成一个“与”联动，并且与第二部分电路中的一个电流开关并联连接的附加晶体管的两个部分电路的耦合形成或门。

公开(公告)号：US3639781A

公开(公告)日：1972-02-01

申请号：US3639781D

申请日：1970-10-26

申请人： FAIRCHILD CAMERA INSTR CO

发明人： MARLEY ROBERT R

IPC分类号： H03K17/62 ,  H03K19/013 ,  H03K19/086 ,  H04J3/04 ,  H03K19/00 ,  H04J3/00

CPC分类号： H03K19/086 ,  H03K17/6264 ,  H03K19/013 ,  H03K19/0866 ,  H04J3/047

摘要： A multiplexer of the series-gated-type wherein the minterms of two variables are generated in positive logic, each of these minterms being used to control one pair of four current path pairs in one level of the multiplexer, is described. Each of the paths in said four pairs of paths controls a separate one of eight inputs in another level of the series gated structure. The gate of another level selects one current path of said selected pair in said one level and thereby selects one of said inputs. A single current source supplies the current for the one-out-ofeight selected current path.

摘要翻译： 描述了串联门控型的多路复用器，其中两个变量的最小值在正逻辑中产生，这些最小值中的每一个用于控制多路复用器的一个电平中的一对四个电流路径对。 所述四对路径中的每个路径控制在串联门控结构的另一个级别中的八个输入中的单独一个。 另一级的门选择所述一级中的所述选择对的一条电流路径，从而选择所述输入之一。 单个电流源为八进制选择的当前路径提供电流。

公开(公告)号：US06380794B1

公开(公告)日：2002-04-30

申请号：US09534522

申请日：2000-03-24

申请人： Navid Foroudi ,  Bent Hessen-Schmidt

发明人： Navid Foroudi ,  Bent Hessen-Schmidt

IPC分类号： H03K1760

CPC分类号： H03K19/09448 ,  H03K19/0866

摘要： A current mode logic circuit having npn transistors coupled to an NMOS current source provides a substantially constant current when controlled by an opamp comparator. A gate of the NMOS current source is directly coupled to an output terminal of the opamp. A source of the NMOS transistor is connected to one of the inputs of the comparator opamp. Another input terminal is connected to voltage source. The opamp compares the two inputs and provides an output signal which ensures that the opamp will provide a substantially constant current source.

摘要翻译： 具有耦合到NMOS电流源的npn晶体管的电流模式逻辑电路在由运算放大器比较器控制时提供基本上恒定的电流。 NMOS电流源的栅极直接耦合到运算放大器的输出端子。 NMOS晶体管的源极连接到比较器运算放大器的一个输入端。 另一个输入端子连接到电压源。 运算放大器比较两个输入，并提供输出信号，确保运算放大器将提供基本恒定的电流源。

公开(公告)号：US5886653A

公开(公告)日：1999-03-23

申请号：US688034

申请日：1996-07-26

申请人： Junichi Ishigami

发明人： Junichi Ishigami

IPC分类号： H03K19/018 ,  H03K19/086 ,  H03K19/20

CPC分类号： H03K19/0866

摘要： Disclosed is a differential decoder circuit, which has: a pair of first and second transistors which form a differential connection, wherein a base of the first transistor is supplied with a reference bias voltage and a base of the second transistor is supplied with an input signal to be decoded to thereby output a decode output depending on the input signal from collector outputs of the first and second transistors; a constant-voltage source; a first bias means for supplying a bias voltage determined by a constant voltage of the constant-voltage source with the base of the first transistor; and a second bias means for supplying the alternative of a voltage determined by the input signal and the voltage determined by the constant voltage depending on a level of the input signal with the base of the second transistor.

摘要翻译： 公开了一种差分解码器电路，其具有：形成差分连接的一对第一和第二晶体管，其中第一晶体管的基极被提供参考偏置电压，并且第二晶体管的基极被提供有输入信号 被解码，从而根据来自第一和第二晶体管的集电极输出的输入信号输出解码输出; 恒压源; 第一偏置装置，用于将由恒压源的恒定电压确定的偏置电压与第一晶体管的基极相提供; 以及第二偏置装置，用于根据与第二晶体管的基极的输入信号的电平，提供由输入信号确定的电压和由恒定电压确定的电压的替代。

公开(公告)号：US5781035A

公开(公告)日：1998-07-14

申请号：US678780

申请日：1996-07-11

申请人： Masakazu Tashibu

发明人： Masakazu Tashibu

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/0866

摘要： A complementary-output vertically-stacked ECL gate circuit is disclosed which is low in power dissipation and fast in operation. The ECL gate circuit has a dual differential pair circuit arrangement provided with a pair of complementary outputs and an active pull-down circuit at each of the outputs. This arrangement allows complementary currents to flow through current switching circuits for the respective differential pair circuits and thus provides complementary outputs with built-in active pull-down circuits.

摘要翻译： 公开了一种互补输出的垂直堆叠的ECL门电路，其功率低并且操作快。 ECL门电路具有双差分对电路布置，在每个输出端设置有一对互补输出和有源下拉电路。 这种布置允许互补电流流过相应差分对电路的电流开关电路，从而提供具有内置有源下拉电路的互补输出。