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    COMPARATOR CIRCUIT WITH INPUT ATTENUATOR
    2.
    发明申请
    COMPARATOR CIRCUIT WITH INPUT ATTENUATOR 有权

    公开(公告)号：US20170302257A1

    公开(公告)日：2017-10-19

    申请号：US15097954

    申请日：2016-04-13

    Applicant: Analog Devices, Inc.

    Inventor： Christopher C. McQuilkin

    IPC: H03K5/24

    CPC classification number: H03K5/2418 ,  H03K5/24 ,  H03K5/2409

    Abstract: A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element.

    Signal amplitude detection circuit
    3.
    发明授权
    Signal amplitude detection circuit 有权
    信号幅度检测电路

    公开(公告)号：US09252760B2

    公开(公告)日：2016-02-02

    申请号：US14459285

    申请日：2014-08-13

    Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.

    Inventor： Ziche Zhang ,  Zhengxian Zou

    IPC: H03D1/00 ,  H03K5/00 ,  H03K5/24

    CPC classification number: H03K5/2409 ,  H03K5/2472

    Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

    Abstract translation: 信号幅度检测电路包括检测器和修整算法模块，检测器具有预设的基准阈值参考值，以及与修整算法模块连接的输出端子，该修整算法模块被布置用于记录和解码检测器的输出结果以输出 并且产生用于控制基准阈值参考值的控制信号从地电平上升到电源电平或从电源电平下降到地电平，并且检测器的输出结果如果 在基准阈值参考值和检测到的信号之间发生交叉; 否则为“0”。 信号幅度检测电路以数字方式检测信号幅度，结构更简单，功耗更低，芯片尺寸减小，无PVT漂移的稳定准确的检测结果。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5477497A

    公开(公告)日：1995-12-19

    申请号：US273745

    申请日：1994-07-12

    Applicant: Hee-choul Park ,  Chul-min Jung

    Inventor： Hee-choul Park ,  Chul-min Jung

    IPC: G11C11/41 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409 ,  G11C11/419 ,  H01L27/10 ,  H03K5/24 ,  H03K5/22

    CPC classification number: G11C7/1057 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1051 ,  H03K5/2409 ,  H03K5/2481

    Abstract: A semiconductor memory device which includes, in a first embodiment, a first PMOS transistor having a source electrode coupled to a signal transport line, a second PMOS transistor having a source electrode coupled to an inverted signal transport line, a drain electrode coupled to a gate electrode of the first PMOS transistor, and a gate electrode coupled to a drain electrode of the first PMOS transistor, a first current limiter connected between the drain electrode of the first PMOS transistor and a reference potential, a second current limiter connected between the drain electrode of the second PMOS transistor and the reference potential, a first constant current source connected between a supply voltage and the source electrode of the first PMOS transistor, and, a second constant current source connected between the supply voltage and the source electrode of the second PMOS transistor.

    Abstract translation: 一种半导体存储器件，其在第一实施例中包括具有耦合到信号传输线的源电极的第一PMOS晶体管，具有耦合到反相信号传输线的源极的第二PMOS晶体管，耦合到栅极的漏电极 第一PMOS晶体管的电极和耦合到第一PMOS晶体管的漏电极的栅电极，连接在第一PMOS晶体管的漏电极和参考电位之间的第一限流器，连接在漏极之间的第二限流器 和连接在第一PMOS晶体管的源极之间的第一恒定电流源，以及连接在第二PMOS晶体管的电源电压和第二PMOS晶体管的源电极之间的第二恒定电流源 晶体管。

    Data reproduction circuit and data transmission device
    7.
    发明授权
    Data reproduction circuit and data transmission device 有权
    数据再生电路及数据传输装置

    公开(公告)号：US09160394B2

    公开(公告)日：2015-10-13

    申请号：US13749414

    申请日：2013-01-24

    Applicant: Sony Corporation

    Inventor： Hideo Morohashi

    IPC: H04L5/16 ,  H04B1/40 ,  H03K5/24 ,  H03K5/08

    CPC classification number: H04B1/40 ,  H03K5/084 ,  H03K5/24 ,  H03K5/2409

    Abstract: Disclosed herein is a data reproduction circuit including: a comparator configured to compare input data resulting from capacitive coupling with a comparison voltage as a threshold voltage and output a comparison result; and a comparison voltage variable section configured to change the comparison voltage along a mark rate of the input data and supply the changed comparison voltage to the comparator.

    Abstract translation: 本文公开了一种数据再现电路，包括：比较器，被配置为将由电容耦合产生的输入数据与比较电压作为阈值电压进行比较，并输出比较结果; 以及比较电压可变部，被配置为沿着输入数据的标记速率改变比较电压，并将改变的比较电压提供给比较器。

    SIGNAL AMPLITUDE DETECTION CIRCUIT
    8.
    发明申请
    SIGNAL AMPLITUDE DETECTION CIRCUIT 有权
    信号放大检测电路

    公开(公告)号：US20150171851A1

    公开(公告)日：2015-06-18

    申请号：US14459285

    申请日：2014-08-13

    Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.

    Inventor： Ziche Zhang ,  Zhengxian Zou

    IPC: H03K5/24

    CPC classification number: H03K5/2409 ,  H03K5/2472

    Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

    Abstract translation: 信号幅度检测电路包括检测器和修整算法模块，检测器具有预设的基准阈值参考值，以及与修整算法模块连接的输出端子，该修整算法模块被布置用于记录和解码检测器的输出结果以输出 并且产生用于控制基准阈值参考值的控制信号从地电平上升到电源电平或从电源电平下降到地电平，并且检测器的输出结果如果 在基准阈值参考值和检测到的信号之间发生交叉; 否则为“0”。 信号幅度检测电路以数字方式检测信号幅度，结构更简单，功耗更低，芯片尺寸减小，无PVT漂移的稳定准确的检测结果。

    Folding comparator compatible with level-crossing sampling
    9.
    发明授权
    Folding comparator compatible with level-crossing sampling 有权
    折叠比较器兼容等级交叉采样

    公开(公告)号：US07839317B1

    公开(公告)日：2010-11-23

    申请号：US12502127

    申请日：2009-07-13

    Applicant: Don Roy Sauer

    Inventor： Don Roy Sauer

    IPC: H03M1/34

    CPC classification number: H03M1/141 ,  H03K5/2409

    Abstract: A Folding Comparator circuit which receives an analog input current and both compares it to a DC reference current while at the same time folding the input current around the reference current to be passed on as an output current which can then be passed on to another folding comparator stage. A series of such stages connected together with some XOR logic gates can perform an analog to digital conversion process as a pipeline of auto-folding stages which will instantly convert analog signal to digital signal.

    Abstract translation: 折叠比较器电路，其接收模拟输入电流，并将其与直流参考电流进行比较，同时将输入电流围绕参考电流折叠以作为输出电流，然后可以传递到另一个折叠比较器 阶段。 与一些XOR逻辑门连接在一起的一系列这样的级可以执行模数转换过程，作为自动折叠级的流水线，其将立即将模拟信号转换成数字信号。

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