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公开(公告)号：US09871530B1
公开(公告)日：2018-01-16
申请号：US15598802
申请日：2017-05-18
申请人： John Howard La Grou
发明人： John Howard La Grou
CPC分类号： H03M7/30 , H03M1/1033 , H03M1/188 , H03M1/68 , H03M5/04
摘要： An analog-to-digital and digital-to-analog conversion system using pulse-density-modulation (PDM) digital signals which minimize noise and optimize dynamic range by dividing a signal into multiple parallel pathways by apportioning a least significant range portion of an incoming signal to a low-path circuit and a most-significant portion of the incoming signal to a high-path circuit. The high-path circuit and low-path circuit can be separately level-modified to optimize dynamic range. Embodiments of the system can include an analog-to-digital conversion, a digital-to-analog conversion, or a complete analog-to-digital and digital-to-analog conversion system.
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公开(公告)号：US09813074B2
公开(公告)日：2017-11-07
申请号：US15470274
申请日：2017-03-27
发明人： Zhang Jun , Xuan Wang , Dongyu Ou , Elliott Zhang , Echo Cao
CPC分类号： H03M1/1033 , H03M1/00 , H03M1/12 , H03M1/685 , H03M1/747
摘要： Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.
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公开(公告)号：US20170201265A1
公开(公告)日：2017-07-13
申请号：US15470274
申请日：2017-03-27
发明人： Zhang Jun , Xuan Wang , Dongyu Ou , Elliott Zhang , Echo Cao
CPC分类号： H03M1/1033 , H03M1/00 , H03M1/12 , H03M1/685 , H03M1/747
摘要： Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.
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4.发明申请公开(公告)号：US20170093415A1
公开(公告)日：2017-03-30
申请号：US15280930
申请日：2016-09-29
申请人： MULTIPHY LTD.
CPC分类号： H03M1/1033 , H03M1/0624 , H03M1/1215
摘要： A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.
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5.发明申请BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN DIGITAL TO ANALOG CONVERTERS 有权背景校正数字到模拟转换器的时序错误公开(公告)号：US20170054447A1
公开(公告)日：2017-02-23
申请号：US15239067
申请日：2016-08-17
申请人： MULTIPHY LTD.
CPC分类号： H03M1/1033 , H03M1/662 , H03M9/00 , H04B17/11 , H04B17/13
摘要： System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.
摘要翻译： 用于校准n级PAM数模转换器（DAC）中的交错时间误差的系统和方法，根据该系统和方法，在DAC的输出端引入一组具有可调取样时间和阈值的两个采样器，它们被分离 及时。 采样器集合通过n单位间隔（UI）窗口扫描，并且n-UI窗口被分类为眼图上的转换和非转换周期。 使用控制环来控制较低速率时钟到n：1多路复用器的相对定时，以在n-UI窗口内强制相等的眼睛宽度，并测量和校正交错的定时误差，直到不均匀分布被降低到低于 一个预定的水平。
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6.发明申请公开(公告)号：US20160212365A1
公开(公告)日：2016-07-21
申请号：US14903153
申请日：2014-07-04
申请人： SONY CORPORATION
发明人： Yuri KATO , Yusuke OIKE
IPC分类号： H04N5/369 , H04N5/378 , H04N5/357 , H04N5/3745
CPC分类号： H04N5/3698 , H03M1/1033 , H03M1/56 , H04N5/357 , H04N5/37455 , H04N5/37457 , H04N5/378
摘要： The present technology relates to a signal processing device and a method, an imaging device, and an imaging apparatus that are designed to reduce occurrences of A/D conversion errors. A signal processing device of the present technology includes: a comparing unit that compares an analog signal output from a unit pixel with a predetermined voltage; a switching unit that switches reference voltages to be supplied to the comparing unit as necessary, connects one of the reference voltages to the comparing unit, and connects another one of the reference voltages to a predetermined load capacitance, the reference voltages being of different gradation accuracies from each other; and a measuring unit that measures timing of a change in a result of the comparison performed by the comparing unit. The present technique can be applied to imaging devices and imaging apparatuses, for example.
摘要翻译： 本技术涉及被设计为减少A / D转换误差的发生的信号处理装置和方法，成像装置和成像装置。 本技术的信号处理装置包括：将从单位像素输出的模拟信号与预定电压进行比较的比较单元; 切换单元，根据需要切换要提供给比较单元的参考电压，将参考电压中的一个连接到比较单元，并将另一个参考电压连接到预定的负载电容，该参考电压具有不同的灰度精度 从彼此; 以及测量单元，其测量由比较单元进行的比较的结果的改变的定时。 例如，本技术可以应用于成像装置和成像装置。
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公开(公告)号：US09369140B1
公开(公告)日：2016-06-14
申请号：US14635155
申请日：2015-03-02
CPC分类号： H03M1/1033 , G01S7/52025 , G01S7/5208 , G11C27/026 , H03M1/1245 , H03M1/1295 , H03M1/466
摘要： An ultrasound probe analog to digital converter includes an input successive approximation register (SAR) first stage; and an output SAR second stage in communication with the input SAR first stage. The input SAR first stage includes a programmable preamplifier integrated therein for residue amplification. The preamplifier is programmed to alternate between a linear amplifier operating mode and a comparator operating mode.
摘要翻译： 超声波探头模数转换器包括输入逐次逼近寄存器（SAR）第一级; 以及与输入SAR第一级通信的输出SAR第二级。 输入SAR第一级包括集成在其中用于残留放大的可编程前置放大器。 前置放大器被编程为在线性放大器工作模式和比较器工作模式之间交替。
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公开(公告)号：US20160109860A1
公开(公告)日：2016-04-21
申请号：US14894654
申请日：2013-05-31
申请人： György Gábor Cserey
IPC分类号： G04F10/00 , H03K3/356 , H03M1/10 , H03K19/177 , H05K7/20
CPC分类号： G04F10/005 , H03K3/356 , H03K19/17748 , H03M1/1033 , H05K7/20
摘要： The invention is a device for determining timing of a measured signal, the device comprising a plurality of flip-flop units (10), each having a clock signal input for receiving the measured signal (20) and a data input for receiving a secondary signal, and an evaluation module being adapted for evaluating outputs of the plurality flip-flop units (10), and the flip-flop units (10) are arranged on an FPGA architecture. The device according to the invention comprises an allocating module for allocating at least one path consisting of flip-flop units (10), wherein the measured signal (20) and the secondary signal are led to the flip-flop units (10) of the at least one path, and a calibration module being adapted for determining a time difference parameter of each flip-flop unit (10), the time difference parameter specifying for each flip-flop unit (10) a time difference between a period of time in which the measured signal (20) reaches the given flip-flop unit (10) from an input point of the measured signal and a period time in which the secondary signal reaches the given flip-flop unit (10) from an input point of the secondary signal, wherein the evaluation module is adapted for determining the timing of the measured signal from the output of the flip-flop units (10) located along the at least one path, on the basis of the time difference parameters. The invention is furthermore a method for determining timing of a measured signal.
摘要翻译： 本发明是一种用于确定测量信号的定时的装置，该装置包括多个触发器单元（10），每个触发器单元具有用于接收测量信号（20）的时钟信号输入端和用于接收辅助信号的数据输入端 ，并且评估模块适于评估多个触发器单元（10）的输出，并且触发器单元（10）被布置在FPGA架构上。 根据本发明的装置包括分配模块，用于分配由触发器单元（10）组成的至少一个路径，其中测量信号（20）和辅助信号被引导到触发器单元（10）的触发器单元（10） 至少一个路径，以及校准模块，用于确定每个触发器单元（10）的时差参数，所述时差参数为每个触发器单元（10）指定时间段之间的时间差 测量信号（20）从测量信号的输入点到达给定的触发器单元（10），以及辅助信号从其输入点到达给定触发器单元（10）的周期时间 辅助信号，其中所述评估模块适于基于所述时差参数来确定来自位于所述至少一个路径的所述触发器单元（10）的输出的测量信号的定时。 本发明还提供了一种用于确定测量信号的定时的方法。
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公开(公告)号：US09258003B2
公开(公告)日：2016-02-09
申请号：US14711200
申请日：2015-05-13
发明人： Takashi Oshima , Tatsuji Matsuura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto , Keisuke Kimura
CPC分类号： H03M1/1033 , H03M1/002 , H03M1/1052 , H03M1/12 , H03M1/201 , H03M1/44 , H03M1/46 , H03M1/66 , H03M1/745
摘要： To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
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公开(公告)号：US09172387B2
公开(公告)日：2015-10-27
申请号：US14479547
申请日：2014-09-08
发明人： Daniel R. Meacham , Andrea Panigada , David Shih
CPC分类号： H03M1/08 , G11C27/02 , G11C27/024 , H03M1/066 , H03M1/1033 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/1225 , H03M1/167 , H03M1/36
摘要： An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2m−1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.
摘要翻译： 模拟输入级具有m个差分输入通道，其中m> 1。 模拟输入级被配置为选择m个差分输入通道之一并提供输出信号。 模拟输入级具有n个相同的选择单元，每个具有m个差分通道输入和一个差分输出，其中n至少为2m-1。 每个选择单元可操作以通过相应的差分多路复用器单元耦合到任何差分输入通道，其中多路复用器单元被驱动以选择差分输入通道中的一个，并通过蝶形开关单元将所选择的差分通道输入与差分 输出选择单元。 组合n个选择单元的差分输出信号，从而通过消除去除除了所选频道以外的信道的不希望的串扰。
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