-
公开(公告)号：US09991902B2
公开(公告)日：2018-06-05
申请号：US15633474
申请日：2017-06-26
发明人： Jinda Yang , Liren Zhou
CPC分类号： H03M1/747 , G06F1/10 , G10L15/12 , H03M1/0836 , H03M1/1205 , H03M1/1215 , H03M1/38 , H03M1/42 , H03M1/76
摘要： An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
-
公开(公告)号：US20170222654A1
公开(公告)日：2017-08-03
申请号：US15407334
申请日：2017-01-17
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Ben Peng XUN , Fei LIU , Meng Meng GUO , Hua TANG , Haifeng YANG
摘要： The present disclosure provides asynchronous successive approximation register analog-to-digital convener (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.
-
3.发明授权公开(公告)号：US09685973B2
公开(公告)日：2017-06-20
申请号：US15285086
申请日：2016-10-04
发明人： Kai-Yin Liu , Che-Wei Chang , Sheng-Hsiung Lin , Shih-Hsiun Huang
摘要： A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.
-
公开(公告)号：US09397955B2
公开(公告)日：2016-07-19
申请号：US14246005
申请日：2014-04-04
申请人： Maxlinear, Inc.
发明人： Curtis Ling
IPC分类号： H04L12/933
CPC分类号： H04L49/101 , H03M1/42 , H04L5/26 , H04L49/206 , H04Q11/0001
摘要： Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer.
摘要翻译： 用于模拟交叉开关的方法和系统可以包括在包括具有模拟交叉开关的接收机路径的无线设备中：接收包括多个信道的数字信号; 放大接收信号; 将放大的信号转换成模拟信号; 将模拟信号分离成多个单独的通道; 使用模拟交叉开关将多个单独的通道路由到期望的信号路径; 以及将路由的多个单独信道转换成多个数字信号。 模拟交叉开关可以包括互补金属氧化物半导体（CMOS）晶体管的阵列。 模拟交叉开关可以包括多个差分对信号线和多个单端信号线。 接收的信号可以利用低噪声放大器（LNA）进行放大，其中LNA的增益电平可以是可配置的。 模拟信号可以使用信道化器分离成单独的信道。
-
5.发明申请Asynchronous Low-Power Analog-to-Digital Converter Circuit With Configurable Thresholds 审中-公开具有可配置阈值的异步低功耗模数转换器电路公开(公告)号：US20160197618A1
公开(公告)日：2016-07-07
申请号：US15067058
申请日：2016-03-10
申请人： Ryan M. FIELD
发明人： Ryan M. FIELD
摘要： An analog-to-digital converter circuit is described that includes register space to keep one or more values to establish upper and lower thresholds of the analog-to-digital converter. The analog-to-digital converter circuit also includes first and second comparators to compare an analog input signal against the upper and lower thresholds and to trigger an analog-to-digital conversion process in response to the analog input signal crossing one of the thresholds. The analog-to-digital converter circuit also includes first logic circuitry to discard a result of the analog-to-digital conversion process if the result is within a prior analog-to-digital conversion process's thresholds. The analog-to-digital converter circuit also includes second logic circuitry to provide the result as an output and generate an interrupt if the result is not within the prior analog-to-digital conversion process's thresholds.
摘要翻译： 描述了一种模数转换器电路，其包括用于保持一个或多个值以建立模数转换器的上限和下限阈值的寄存器空间。 模数转换器电路还包括用于将模拟输入信号与上限和下限阈值进行比较的第一和第二比较器，并且响应于模拟输入信号跨过阈值之一触发模数转换过程。 如果结果在先前的模数转换过程的阈值之内，则模数转换器电路还包括第一逻辑电路，以丢弃模数转换过程的结果。 模数转换器电路还包括第二逻辑电路，以将结果提供为输出，并且如果结果不在先前的模数转换过程的阈值内，则产生中断。
-
公开(公告)号：US20150061913A1
公开(公告)日：2015-03-05
申请号：US14016948
申请日：2013-09-03
发明人： Xiaodong Wang , Shouli Yan , Axel Thomsen
IPC分类号： H03M1/42
摘要： A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.
摘要翻译： 一种方法包括在比较器的第一和第二输入处接收差分电压信号，并且在转换阶段期间选择性地将差分电压信号提供给比较器的第一转换路径和第二转换路径中的一个，以确定对应于 差分电压信号。 第一和第二转换路径分别包括第一和第二多个增益级。 该方法还包括将所选择的第一转换路径和第二转换路径中的一个耦合到输出以提供数字值。
-
公开(公告)号：US20140301413A1
公开(公告)日：2014-10-09
申请号：US14246005
申请日：2014-04-04
申请人： Maxlinear, Inc.
发明人： Curtis Ling
IPC分类号： H04L12/933
CPC分类号： H04L49/101 , H03M1/42 , H04L5/26 , H04L49/206 , H04Q11/0001
摘要： Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer.
摘要翻译： 用于模拟交叉开关的方法和系统可以包括在包括具有模拟交叉开关的接收机路径的无线设备中：接收包括多个信道的数字信号; 放大接收信号; 将放大的信号转换成模拟信号; 将模拟信号分离成多个单独的通道; 使用模拟交叉开关将多个单独的通道路由到期望的信号路径; 以及将路由的多个单独信道转换成多个数字信号。 模拟交叉开关可以包括互补金属氧化物半导体（CMOS）晶体管的阵列。 模拟交叉开关可以包括多个差分对信号线和多个单端信号线。 接收的信号可以利用低噪声放大器（LNA）进行放大，其中LNA的增益电平可以是可配置的。 模拟信号可以使用信道化器分离成单独的信道。
-
公开(公告)号：US08847811B2
公开(公告)日：2014-09-30
申请号：US13369093
申请日：2012-02-08
IPC分类号： H03M1/34
摘要： Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.
摘要翻译： 提供了使用串行纹波模数转换（ADC）将模拟信号转换为数字输出信号的示例。 ADC电路可以包括串联耦合的转换级。 每个转换级可以产生数字输出信号的位。 数据锁存器可以接收来自转换级的数字输出信号的位，并且基于位提供数字输出信号。 转换级可以包括比较器电路和多路复用器电路。 比较器电路可以将采样的输入信号与参考信号进行比较，并且基于比较的结果产生数字输出信号的相关位。 多路复用器电路可以向下一个转换级的比较器电路提供相关联的参考信号，其中下一个转换级在转换级之后。
-
公开(公告)号：US08483343B2
公开(公告)日：2013-07-09
申请号：US12056084
申请日：2008-03-26
申请人： Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
发明人： Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03M1/0626 , H03M1/0692 , H03M1/0695 , H03M1/1042 , H03M1/1215 , H03M1/181 , H03M1/42 , H03M1/44 , H04L7/0004 , H04L7/0062 , H04L7/0087 , H04L25/0204 , H04L25/03038
摘要： A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
摘要翻译： 接收机（例如，用于10G光纤通信链路）包括耦合到多通道均衡器的交错ADC，其可以为交错ADC内的不同ADC通道提供不同的均衡。 也就是说，多通道均衡器可以补偿信道相关的损伤。 在一种方法中，多信道均衡器是耦合到维特比解码器（例如滑块维特比解码器（SBVD））的前馈均衡器（FFE）; 并且使用LMS算法适配维特比解码器的FFE和/或信道估计器。
-
公开(公告)号：US07098840B2
公开(公告)日：2006-08-29
申请号：US11172511
申请日：2005-06-30
申请人： Antonello Arigliano
发明人： Antonello Arigliano
IPC分类号： H03M1/12
摘要： The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks, comparable to a domino structure. One key advantage of the domino ASA ADC is its modular structure; each block is independent from all others. The unity capacitors used need to be matched only within their specific blocks. The architecture is very flexible; it is possible to increase the resolution by adding more blocks of the same kind. The ASA ADC is very fast, its speed is only limited the RC constants during the sampling and measurement phase and the speed of the comparators used.
摘要翻译： 多米诺异步逐次逼近（ASA）模数转换器（ADC）将模拟信号转换为n位数字信号。 多米诺骨牌ASA ADC由n个块组成，对应于数字输出的n位数。 这些n块中的每一个产生转换位，并校准所有后续块，与多米诺骨牌结构相当。 domino ASA ADC的一个关键优点是其模块化结构; 每个块独立于所有其他块。 所使用的单位电容仅需要在其特定的块内进行匹配。 该架构非常灵活; 可以通过添加更多相同的块来提高分辨率。 ASA ADC非常快，其速度仅限于采样和测量阶段的RC常数以及所用比较器的速度。
-
-
-
-
-
-
-
-
-
搜索结果
159 条记录 (耗时 0.024 秒)