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公开(公告)号：US10007235B2
公开(公告)日：2018-06-26
申请号：US15711012
申请日：2017-09-21
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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公开(公告)号：US10003353B2
公开(公告)日：2018-06-19
申请号：US15652710
申请日：2017-07-18
发明人： Bryan Kris , Jim Bartling , Neil Deutscher
CPC分类号： H03M1/502 , H03K5/14 , H03K5/24 , H03M1/1205
摘要： Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.
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公开(公告)号：US20170373698A1
公开(公告)日：2017-12-28
申请号：US15685447
申请日：2017-08-24
发明人： Hao YAN , Jiale Huang , Lei Lu
CPC分类号： H03M1/002 , G04F10/005 , H03L7/0814 , H03M1/502
摘要： A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.
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公开(公告)号：US09806733B1
公开(公告)日：2017-10-31
申请号：US15339200
申请日：2016-10-31
发明人： Martin Kinyua
CPC分类号： H03M1/124 , G04F10/005 , H03M1/1023 , H03M1/164 , H03M1/502 , H04N5/378
摘要： An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.
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公开(公告)号：US20170310334A1
公开(公告)日：2017-10-26
申请号：US15507704
申请日：2015-09-02
发明人： Shuo-Wei Chen
CPC分类号： H03M1/1245 , H03M1/0609 , H03M1/10 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.
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公开(公告)号：US09729162B1
公开(公告)日：2017-08-08
申请号：US15223310
申请日：2016-07-29
发明人： Wenhuan Yu , Abdulkerim L. Coban
CPC分类号： H03M1/0617 , H03F3/45183 , H03F3/45475 , H03F3/45636 , H03F3/45659 , H03F2200/267 , H03F2203/45022 , H03F2203/45222 , H03F2203/45418 , H03F2203/45424 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45591 , H03H11/04 , H03H11/0422 , H03H11/1213 , H03K5/1252 , H03M1/00 , H03M1/12 , H03M1/145 , H03M1/502
摘要： In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.
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公开(公告)号：US20170187978A1
公开(公告)日：2017-06-29
申请号：US15455270
申请日：2017-03-10
申请人： OLYMPUS CORPORATION
发明人： Yoshio Hagihara
IPC分类号： H04N5/376 , H04N5/3745 , H03M7/30 , H03K5/15 , H03M1/20
CPC分类号： H04N5/3765 , H03K5/15066 , H03M1/123 , H03M1/20 , H03M1/502 , H03M1/56 , H03M7/30 , H04N5/3745 , H04N5/378
摘要： An encoding circuit includes a clock generating unit having a delay circuit in which n (n is a power of 2) delay units are connected together a latch unit configured to latch the plurality of delayed signals; and an encoding unit configured to encode state of each of the plurality of delayed signals, wherein the encoding unit encodes the state of each of the plurality of delayed signals by performing: a first operation of determining a position at which logic states of two or more delayed signals in a signal group change from High to Low, a second operation of determining a position at which logic states of two or more delayed signals in the signal group change from Low to High, and a third operation of determining that logic states of two or more signals including at least one delayed signal in the signal group are predetermined states.
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公开(公告)号：US09483028B1
公开(公告)日：2016-11-01
申请号：US15099460
申请日：2016-04-14
发明人： Martin Kinyua
CPC分类号： H03M1/124 , G04F10/005 , H03M1/1023 , H03M1/164 , H03M1/502 , H04N5/378
摘要： An analog-to-digital converter (ATC) circuit includes a current source; a first amplifier coupled to the current source through a first discharging switch; and a second amplifier coupled to the first amplifier through a second discharging switch; wherein the first amplifier is configured to receive a residue signal of an analog input signal, upon the first discharging switch being turned on, the first amplifier amplifies the residue signal to generate an output signal and simultaneously the current source discharges the residue signal, upon the second discharging switch being turned on, the second amplifier detects when the output signal equals zero so as to determine a discharging time duration of the output signal.
摘要翻译： 模拟 - 数字转换器（ATC）电路包括电流源; 第一放大器，通过第一放电开关耦合到电流源; 以及通过第二放电开关耦合到所述第一放大器的第二放大器; 其中所述第一放大器被配置为在所述第一放电开关导通时接收模拟输入信号的残留信号，所述第一放大器放大所述残留信号以产生输出信号，并且同时所述电流源对所述残留信号进行放电， 第二放大开关导通，第二放大器检测输出信号何时等于零，以便确定输出信号的放电持续时间。
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9.发明授权Integrating A/D converter, integrating A/D conversion method, solid-state imaging device and camera system 有权集成A / D转换器，集成A / D转换方法，固态成像装置和相机系统公开(公告)号：US09204070B2
公开(公告)日：2015-12-01
申请号：US13064910
申请日：2011-04-26
摘要： An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.
摘要翻译： 积分A / D转换器包括：比较输入电压与具有斜坡波形的参考电压的比较器，其电压值随时间线性变化; 通过比较器的输出信号的反相触发的高位位计数器启动操作或停止操作，并通过在时钟信号的周期中进行计数来输出高位位; 以及时间 - 数字转换器，其锁存与通过延迟比较器的输出信号而获得的多个信号相对应的时钟信号的相位信息，并对锁存的值进行解码以输出比时钟周期更高的分辨率的低阶位。
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公开(公告)号：US20150212494A1
公开(公告)日：2015-07-30
申请号：US14681206
申请日：2015-04-08
发明人： Mikko Waltari
CPC分类号： G04F10/005 , H03M1/1295 , H03M1/50 , H03M1/502 , H03M1/60
摘要： A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal.
摘要翻译： 提供了一种将时间敏感信号转换为数字值的行波脉冲波量化方法。 第一停止信号被延迟第一时间延迟，第一次多次，以产生延迟的第一停止信号。 时钟信号被延迟第二时间延迟，第一次多次，以产生延迟的时钟信号第一周期。 每个第二时间延迟与对应的第一时间延迟相关联，并且第二时间延迟大于第一时间延迟。 当延迟的第一停止信号在延迟时钟信号第一周期之前发生时，延迟的计数被停止并转换成数字或温度计值。 无论第一停止信号和第一停止信号之后接受的第二停止信号的延迟持续时间如何，均提供精确的重采样值。
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