摘要:
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
摘要:
Provided is an information reconciliation method in a quantum key distribution system between a transmitter and a receiver, which includes receiving a parity bit from the transmitter through a quantum channel, correcting an error of a receiver quantum key by using the received parity bit, and removing a residual error of the receiver quantum key through an open channel by using a cascade protocol to harmonize the receiver quantum key with a transmitter quantum key, wherein the parity bit is generated at the transmitter by using turbo codes. This method may enhance quantum key generation efficiency.
摘要:
A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.
摘要:
LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).
摘要:
A Low Density Parity Check (LDPC) code encoding apparatus for a communication system is provided. The encoding apparatus receives information bits, and generates an LDPC code by encoding the information bits using an interleaving scheme. The interleaving scheme is generated such that when the LDPC code is punctured, there is no short-length cycle in a Tanner graph of the punctured LDPC code.
摘要:
A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix; transmitting the codeword generated by using the generator matrix to another communications device; generating, when the communications device receives a NAK in response to the codeword, a first additional parity by using the second parity check matrix; and retransmitting the first additional parity to the another communications device.
摘要:
A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.
摘要:
A method for generating a parity check matrix of a block LDPC code. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity. The method includes determining a size of the parity check matrix based on a coding rate applied when coding the information word with the block LDPC code, and a codeword length; dividing a parity check matrix with the determined size into a predetermined number of blocks; classifying the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; arranging permutation matrixes in predetermined blocks from among the blocks classified as the first parity part, and arranging identity matrixes in a full lower triangular form in predetermined blocks from among the blocks classified as the second parity part; and arranging the permutation matrixes in the blocks classified as the information part such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code.
摘要:
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
摘要:
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.