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    Generating Cryptographic Checksums
    2.
    发明申请
    Generating Cryptographic Checksums 审中-公开

    公开(公告)号：US20180069706A1

    公开(公告)日：2018-03-08

    申请号：US15558844

    申请日：2015-05-04

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Elena DUBROVA ,  Gunnar MILDH ,  Mats NÄSLUND ,  Göran SELANDER

    IPC分类号： H04L9/32 ,  H03M13/09 ,  H03M13/15 ,  G06F11/10

    CPC分类号： H04L9/3242 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/158 ,  H04L9/3236 ,  H04L2209/34

    摘要： A method (400) of generating a cryptographic checksum for a message M(x) is provided. The method is performed by a communication device, such as a sender or a receiver, and comprises calculating (405) the cryptographic checksum as a first function g of a division of a second function of M(x), f(M(x)), modulo a generator polynomial p(x) of degree n, g(f(M(x)) mod p(x)). The generator polynomial is calculated (403) as p(x)=(1−x)·P1(x), and P/(x) is a primitive polynomial of degree n−1. The primitive polynomial is selected (402), based on a first cryptographic key, from the set of primitive polynomials of degree n−1 over a Galois Field. By replacing a standard checksum with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. The proposed checksum is capable of detecting double-bit errors which may be introduced by a Turbo code decoder.

    ERASURE CODE DATA PROTECTION AND RECOVERY COMPUTATION SYSTEM AND METHOD
    3.
    发明申请
    ERASURE CODE DATA PROTECTION AND RECOVERY COMPUTATION SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20180054217A1

    公开(公告)日：2018-02-22

    申请号：US15431629

    申请日：2017-02-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： William David Schwaderer

    IPC分类号： H03M13/15 ,  G06F11/10 ,  H03M13/00

    CPC分类号： H03M13/154 ,  G06F11/1076 ,  H03M13/15 ,  H03M13/158 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/6502

    摘要： A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.

    Forward error correcting code encoder and decoder method and apparatus
    4.
    发明授权
    Forward error correcting code encoder and decoder method and apparatus 有权
    前向纠错码编码器及解码方法及装置

    公开(公告)号：US09432057B1

    公开(公告)日：2016-08-30

    申请号：US14140125

    申请日：2013-12-24

    申请人： MARVELL INTERNATIONAL LTD.

    发明人： Weishi Feng

    IPC分类号： H03M13/00 ,  H03M13/15 ,  H03M13/03 ,  H03M13/05 ,  H03M13/29

    CPC分类号： H03M13/151 ,  H03M13/1515 ,  H03M13/158 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6561

    摘要： A method includes generating a first subset of codeword symbols by processing, during each of a plurality of iterations, a first input and a second input. The first input is a function of (i) an output, during a respective one of the plurality of iterations, of a last processing stage of a first plurality of processing stages and (ii) a symbol, of a first subset of original symbols, corresponding to the respective iteration. The second input is a function of (i) an output, during the respective iteration, of a last processing stage of the second plurality of processing stages and (ii) a symbol, of a second subset of original symbols, corresponding to the respective iteration. The method also includes generating a second subset of codeword symbols by processing, during each of the plurality of iterations, the first input and the second input.

    摘要翻译： 一种方法包括通过在多个迭代中的每一个期间处理第一输入和第二输入来生成码字符号的第一子集。 第一输入是（i）在多个迭代中的相应一个迭代期间，在第一多个处理阶段的最后一个处理阶段和（ii）原始符号的第一子集的符号的输出， 对应于各自的迭代。 第二输入是（i）在相应迭代期间在第二多个处理阶段的最后处理阶段的输出和（ii）对应于相应迭代的原始符号的第二子集的符号的函数 。 该方法还包括通过在多个迭代中的每一个期间处理第一输入和第二输入来生成码字符号的第二子集。

    Error location search circuit, and error check and correction circuit and memory device including the same
    5.
    发明授权
    Error location search circuit, and error check and correction circuit and memory device including the same 有权
    错误位置搜索电路，以及错误检查和校正电路和包含相同的存储器件

    公开(公告)号：US09384083B2

    公开(公告)日：2016-07-05

    申请号：US14034803

    申请日：2013-09-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Daisuke Fujiwara ,  Makoto Hirano

    IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/07 ,  H03M13/15

    CPC分类号： G06F11/10 ,  H03M13/07 ,  H03M13/1545 ,  H03M13/158 ,  H03M13/6561

    摘要： Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2n) and a value of (n-k)-bit, and calculate a second bit string by multiplying the plurality of elements and a value of k-bit; and a plurality of Chien search circuits configured to combine the first bit string and the second bit string to calculate the arbitrary element. The plurality of Chien search circuits are arranged in a matrix along a row direction and a column direction. The first bit string is provided in the row direction or the column direction, and the second bit string is provided in a direction different from the direction of the first bit string.

    摘要翻译： 提供了一种错误检查和校正（ECC）电路，其包括被配置为确定数据串中是否存在错误的Chien搜索单元。 Chien搜索单元包括被配置为通过乘以伽罗瓦域GF（2n）的多个元素和（nk）比特的值来计算第一比特串的电路，并且通过将多个元素相乘来计算第二比特串， k位的值; 以及多个Chien搜索电路，被配置为组合第一位串和第二位串以计算任意元素。 多个Chien搜索电路沿着行方向和列方向排列成矩阵。 第一位串被设置在行方向或列方向上，并且第二位串被设置在与第一位串的方向不同的方向上。

    N-valued shift registers with inverter reduced feedback logic functions
    7.
    发明授权
    N-valued shift registers with inverter reduced feedback logic functions 有权
    具有变频器的N值移位寄存器减少反馈逻辑功能

    公开(公告)号：US09218158B2

    公开(公告)日：2015-12-22

    申请号：US14622860

    申请日：2015-02-14

    申请人： Peter Lablans

    发明人： Peter Lablans

    IPC分类号： G06F7/487 ,  H03M7/00 ,  H04L9/06 ,  G06F5/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H03M13/23

    CPC分类号： G06F7/4876 ,  G06F5/012 ,  H03M7/00 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/158 ,  H03M13/19 ,  H03M13/23 ,  H04L9/06

    摘要： Shift register based circuits include non-binary polynomial calculation circuits, coder circuits, scramblers, descramblers and sequence generators that apply non-binary two-input/single output switching functions wherein at least one input contains a non-binary inverter or multiplier. A combination of a two-input/single output non-binary switching device with at least one non-binary inverter at an input is advantageously reduced to a single device that implements a single non-binary switching function. The reduced single device may be an electronic memory that stores the truth table of the single non-binary switching function.

    摘要翻译： 基于移位寄存器的电路包括非二进制多项式计算电路，编码器电路，加扰器，解扰器和序列发生器，其应用非二进制双输入/单输出开关功能，其中至少一个输入包含非二进制反相器或乘法器。 两输入/单输出非二进制开关器件与输入端的至少一个非二进制反相器的组合有利地被简化为实现单个非二进制开关功能的单个器件。 减少的单个设备可以是存储单个非二进制切换功能的真值表的电子存储器。

    ERROR CORRECTION CODE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    9.
    发明申请
    ERROR CORRECTION CODE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权
    错误校正代码电路和包括其的存储器件

    公开(公告)号：US20140108895A1

    公开(公告)日：2014-04-17

    申请号：US14054190

    申请日：2013-10-15

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Daisuke FUJIWARA

    IPC分类号： H03M13/07

    CPC分类号： H03M13/1545 ,  G06F11/08 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/04 ,  H03M13/1148 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/153 ,  H03M13/154 ,  H03M13/1575 ,  H03M13/158 ,  H03M13/19 ,  H03M13/3707 ,  H03M13/6566

    摘要： The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value.

    摘要翻译： ECC电路包括被配置为确定数据序列的每个比特是否存在错误的Chien搜索单元。 Chien搜索单元从误差定位多项式的项中选择非线性项的系数作为非线性系数，将误差定位多项式分离为仅包括线性项的第一位置方程和仅包括非线性项的第二位置方程，确定 通过将第一位置方程除以非线性系数的第三位置方程通过将第二位置方程除以非线性系数来确定第四位置方程，并且通过对结果执行异或运算来确定是否存在针对每个位的错误 使用替代值的第三位置方程和使用误差定位多项式的任意元素作为替代值的第四位置方程的结果。