公开(公告)号：US09935890B2

公开(公告)日：2018-04-03

申请号：US15092696

申请日：2016-04-07

申请人： Panasonic Corporation

发明人： Peter Klenner

IPC分类号： H04L12/863 ,  H03M13/27 ,  H04L1/00

CPC分类号： H04L47/6245 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2785 ,  H03M13/2796 ,  H04L1/0071 ,  H04L1/0076 ,  H04L1/0085 ,  H04L47/6255

摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a first connection destination of an input terminal of the convolutional interleaver to one end of one of a plurality of branches; a plurality of FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a second connection destination of an output terminal of the convolutional interleaver to the other end of one of the plurality of branches. The first and second switches switch the first and second connection destinations, respectively, when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the first and second connection destinations sequentially and repeatedly among the plurality of branches.

公开(公告)号：US09842048B2

公开(公告)日：2017-12-12

申请号：US14939863

申请日：2015-11-12

申请人： iBiquity Digital Corporation

发明人： Marek Milbar

IPC分类号： H04L27/06 ,  G06F12/06 ,  H03M13/27 ,  H03M13/00 ,  H04L27/26 ,  H04B1/06 ,  H04W52/02

CPC分类号： G06F12/0607 ,  G06F2212/1028 ,  G06F2212/154 ,  G06F2212/174 ,  H03M13/2707 ,  H03M13/2785 ,  H03M13/6569 ,  H04B1/06 ,  H04H2201/18 ,  H04L27/2601 ,  H04L27/2649 ,  H04W52/0206 ,  Y02D70/164

摘要： A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a n×k addresses, wherein the block comprises a single table, receiving a digital radio broadcast signal at the receiver, and demodulating the digital radio broadcast signal into a plurality of interleaved data units. For at least one series of n×k data units a pointer step size is determined, and for each data unit in the series, an address in the block is calculated based on the pointer step size, and an output data unit is read from the block at the address, such that said output data units represent block deinterleaved data units. An input data unit from the plurality of interleaved data units is then written to the block at the address. Associated systems and computer readable storage media are presented.

公开(公告)号：US20120054578A1

公开(公告)日：2012-03-01

申请号：US13293231

申请日：2011-11-10

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： H03M13/2957 ,  H03M13/2757 ,  H03M13/2785 ,  H03M13/3972 ,  H03M13/6566 ,  H04L1/0071

摘要： Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, (MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.

摘要翻译： 具有二次多项式置换（QPP）交错的并行涡轮解码的公式灵活无冲突存储器存取。 提出了一种可以使用任何期望数量的并行实施的turbo解码处理器来执行已经使用QPP交织进行的turbo解码的装置。 呈现该方法以允许任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）在仍然使用QPP交织的所选实施例的情况下执行turbo编码信号的解码。 此外，无冲突存储器映射（MOD，C，W）提供了更多的自由度，用于选择满足具有任何所需数量的并行实现的turbo的并行turbo解码实现的特定二次多项式置换（QPP）交织（＆pgr） 解码处理器。 该存储器映射允许将更新的信息（使用并行实现的turbo解码器更新）的无冲突读写写入存储体。

公开(公告)号：US20100245677A1

公开(公告)日：2010-09-30

申请号：US12726484

申请日：2010-03-18

申请人： Takashi YOKOKAWA ,  Hitoshi Sakai

发明人： Takashi YOKOKAWA ,  Hitoshi Sakai

IPC分类号： H03M13/05 ,  H04N5/44 ,  G06F11/10

CPC分类号： H03M13/11 ,  H03M13/2707 ,  H03M13/2785 ,  H03M13/2789

摘要： A receiving apparatus includes: a deinterleaving device configured to perform a deinterleaving process on an LDPC-coded data signal having undergone an interleaving process, the LDPC representing Low Density Parity Check, by use of a memory which has columns capable of storing as many as “a” data, the “a” being an integer of at least 1; and a control device configured such that if the data signal is supplied in units of N data, the N being an integer smaller than the “a,” the control device controls the deinterleaving device to write the data signal to a predetermined address of the memory while reading previously written data from the predetermined address in a write period, the control device further controlling the deinterleaving device to stop writing the data signal to the predetermined address of the memory while reading the previously written data from the predetermined address in a write inhibit period.

摘要翻译： 接收装置包括：解交织装置，被配置为对已经经历交织处理的LDPC编码数据信号执行解交织处理，LDPC表示低密度奇偶校验，通过使用具有能够存储多达“ “数据”，“a”为至少1的整数; 以及控制装置，被配置为使得如果以N个数据为单位提供数据信号，则N是小于“a”的整数，控制装置控制解交织装置将数据信号写入存储器的预定地址 同时在写周期期间从预定地址读取先前写入的数据时，控制装置进一步控制解交错装置，以便在写入禁止期间从预定地址读出先前写入的数据时停止将数据信号写入存储器的预定地址 。

公开(公告)号：US20100077282A1

公开(公告)日：2010-03-25

申请号：US12627438

申请日：2009-11-30

申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

IPC分类号： H03M13/25 ,  H03M13/03 ,  G06F11/08 ,  G06F11/10

CPC分类号： H04L1/005 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H04L1/0055 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

摘要翻译： TTCM（Turbo Trellis编码调制）的可变速率和信号星座的真位解码。 提出了一种解码方法，其允许基于比特级的解码，其允许区分符号的各个比特。 而现有技术方法通常在符号级基础上执行解码，这种解码方法允许改进的方法，其中可以针对信息符号的各个比特分别进行硬判决/最佳估计。 此外，解码方法允许减少需要执行的计算的总数以及在迭代解码期间需要存储的值的总数。 比特级解码方法还能够解码其码率和/或信号星座类型（和映射）可以在逐个符号的基础上变化的信号。

公开(公告)号：US07519872B2

公开(公告)日：2009-04-14

申请号：US10971163

申请日：2004-10-25

申请人： Jeong-taek Lee

发明人： Jeong-taek Lee

IPC分类号： G06F11/00

CPC分类号： H04H40/18 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2782 ,  H03M13/2785 ,  H04H20/426 ,  H04H2201/20

摘要： Disclosed is a deinterleaving device and method for digital broadcast receivers having a downsized deinterleaver memory. The deinterleaving device includes a memory having storage space for performing the deinterleaving in a number of deinterleaving units over the K groups of input data in correspondence with an interleaving unit at a transmitter; an address generator for reading data written in the memory and generating memory addresses for writing input data; read-enable unit and write-enable unit for reading and writing data written at the generated memory addresses; and a controller for controlling the address generator to generate the memory addresses for the input data in correspondence with the deinterleaving units, the controller controlling the read-enable unit and the write-enable unit to read data written at the memory addresses before writing the input data at the memory addresses.

摘要翻译： 公开了一种具有小型解交织器存储器的数字广播接收机的解交织设备和方法。 解交织装置包括：具有存储空间的存储器，用于在与发送器处的交织单元对应的K组输入数据上执行多个解交织单元中的去交织; 用于读取写入存储器中的数据并产生用于写入输入数据的存储器地址的地址发生器; 读取使能单元和写入使能单元，用于读取和写入在所生成的存储器地址上写入的数据; 以及控制器，用于控制地址发生器以与解交错单元相对应地生成用于输入数据的存储器地址，控制器控制读取使能单元和写入使能单元在写入输入之前读取写入存储器地址的数据 数据在存储器地址。

公开(公告)号：US07451378B2

公开(公告)日：2008-11-11

申请号：US11623617

申请日：2007-01-16

申请人： Rajugopal Gubbi ,  Javaji Sunil Babu ,  Ramanujan K Valmiki

发明人： Rajugopal Gubbi ,  Javaji Sunil Babu ,  Ramanujan K Valmiki

IPC分类号： H03M13/00

CPC分类号： H03M13/2785 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/6356 ,  H03M13/6362

摘要： Systems and methods are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows, the addresses for the entries in the receive buffer being arranged sequentially in column-major order; (b) a first process writing MPE data into the receive buffer, in the manner such that, for each frame, the application data portion and the error correction code portion are written sequentially in column major order, (c) a second process decoding the error correction code portion of each frame and which corrects the application data portion in accordance with the decoding; and (d) a third process reading out the application data portion from the receiver buffer column by column, the third process re-reading any column of the application portion that is corrected by the second process, when that column has previously been read by the third process.

摘要翻译： 提供了用于处理DVB-H标准下的多协议封装（MPE）的系统和方法。 该系统包括：（a）具有组织为列和行的条目的接收缓冲器，接收缓冲器中的条目的地址按列主要顺序排列; （b）将MPE数据写入接收缓冲器的第一过程，以对于每个帧的方式，应用数据部分和纠错码部分以列主要顺序被顺序地写入，（c）第二处理解码 每个帧的纠错码部分，并根据解码校正应用数据部分; 和（d）第三进程逐列从接收器缓冲器读出应用数据部分，第三进程重新读取由第二进程校正的应用部分的任何列，当该列先前被 第三个过程。

公开(公告)号：US20070220406A1

公开(公告)日：2007-09-20

申请号：US11623617

申请日：2007-01-16

申请人： Rajugopal Gubbi ,  Javaji Babu ,  Ramanujan Valmiki

发明人： Rajugopal Gubbi ,  Javaji Babu ,  Ramanujan Valmiki

IPC分类号： H03M13/00

CPC分类号： H03M13/2785 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/6356 ,  H03M13/6362

摘要： A system and a method are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows and in which the addresses for the entries in the receive buffer are arranged sequentially in column-major order; (b) a first process writing MPE data into the receive buffer, in the manner such that, for each frame, the application data portion and the error correction code portion are written sequentially in column major order, (c) a second process decoding the error correction code portion of each frame and which corrects the application data portion in accordance with the decoding; and (d) a third process reading out the application data portion from the receiver buffer column by column, the third process re-reading any column of the application portion that is corrected by the second process, when that column has previously been read by the third process. Under this system, the first process (a) keeps tracks of the locations of the MPE data of each frame in the receive buffer in a mapping table, and (b) writes the MPE data of a next frame is written into the locations of the error correcting code portion of a previous frame, when the locations become available.

摘要翻译： 提供了一种用于处理DVB-H标准下的多协议封装（MPE）的系统和方法。 该系统包括：（a）具有组织为列和行的条目的接收缓冲器，其中接收缓冲器中的条目的地址按列主序列顺序排列; （b）将MPE数据写入接收缓冲器的第一过程，以对于每个帧的方式，应用数据部分和纠错码部分以列主要顺序被顺序地写入，（c）第二处理解码 每个帧的纠错码部分，并根据解码校正应用数据部分; 和（d）第三进程逐列从接收器缓冲器读出应用数据部分，第三进程重新读取由第二进程校正的应用部分的任何列，当该列先前被 第三个过程。 在该系统下，第一过程（a）在映射表中保持接收缓冲器中每帧的MPE数据的位置的轨迹，并且（b）将下一帧的MPE数据写入到 当位置变得可用时，纠错前一帧的代码部分。

公开(公告)号：US20070016841A1

公开(公告)日：2007-01-18

申请号：US11491729

申请日：2006-07-24

申请人： Kelly Cameron ,  Ba-Zhong Shen ,  Hau Tran

发明人： Kelly Cameron ,  Ba-Zhong Shen ,  Hau Tran

IPC分类号： H03M13/00

CPC分类号： H04L1/005 ,  G11B20/18 ,  H03M13/1102 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H03M13/45 ,  H04L1/0041 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single TTCM decoder is operable to decode each of the various rates at which the data is encoded by the TTCM encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

摘要翻译： 可变码率和信号星座turbo网格编码调制（TTCM）编解码器。 在通信系统（编码器和解码器）的两端采用通用网格，以不同速率对数据进行编码和解码。 该编码采用单个TTCM编码器，其输出位可以根据速率控制序列被选择性地打孔以支持多种调制（星座和映射）。 单个TTCM解码器可操作以解码由TTCM编码器编码数据的各种速率的每一个。 速率控制序列可以包括在编码和解码期间重复的周期中布置的速率控制的数量。 编码器和解码器中的一个或两者可以基于通信系统的操作条件（诸如信噪比（SNR）的变化）来自适应地选择新的速率控制序列。

公开(公告)号：US07107512B2

公开(公告)日：2006-09-12

申请号：US10444148

申请日：2003-05-22

申请人： Kelly Brian Cameron

发明人： Kelly Brian Cameron

IPC分类号： H03M13/03

CPC分类号： H04L1/005 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： TTCM (Turbo Trellis Coded Modulation) decoder design. The design also adapts to any number of devices that perform decoding of Trellis Code Modulation (TCM) signals. After performing initial symbol processing within a data block to generate a number of check point values, the design selectively re-calculates some forward metrics (alphas) and backward metrics (betas), and the design is able to calculate extrinsic (ext) information for each symbol within the data block successively. The data block is subdivided into a number of sub-blocks that are intelligently processed to enable extremely fast processing. Generally speaking, the design performs initial processing starting from both block ends, and upon approaching the block middle, the design begins to process the block using skip backs to previous sub-blocks. The design employs a great deal of parallel and simultaneously processing to provide for very fast computation of the various values required to decode the block.