摘要:
In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
摘要:
A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
摘要:
The invention related to a turbo decoder comprising SISO decoding modules each other interconnected in a feedback control scheme having scaling modules for applying a scaling factor to extrinsic information delivered by said SISO decoding modules. The turbo decoder comprises a selection module for adaptively selecting said scaling factor based on a number of decoding iterations of the turbo decoder.
摘要:
In a normalization process, overflow occurring in limited size registers, holding the alpha or beta values in a map decoder, may be overcome by subtracting a constant value from all of the alpha or beta values when they reach a limit. Because subtracting a constant value may slow down the computation, detection of a constant value may occur on one decoding cycle and normalization on the succeeding decoding cycle. A multiplexor type circuit can be used to direct either zeros, in the normalization case, or a most significant bit(s), in computations without normalization, into the register holding the alpha or beta values. To minimize the impact on the computation by the normalization process, the multiplexor circuit can be set by the previous decoder cycle so that the computation does not have to wait for the multiplexor to be set to normalization or normal computation.
摘要:
A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.
摘要:
A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.
摘要:
A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.
摘要:
A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.
摘要:
When an information length N is divided by a division length L, if the number of divisions including the remainder is 2n, then backward probabilities are calculated from the Nth backward probability in the reverse direction to the (n+1)th section and backward probabilities at division points are stored as discrete values, and in parallel with these backward probability calculations, forward probabilities are calculated from the first forward probability in the forward direction to the nth section and the forward probabilities at division points are stored as discrete values. Subsequently, the backward probabilities and forward probabilities stored as discrete values are used to calculate backward probabilities and forward probabilities for each section, and using these probabilities, decoding results are calculated in sequence for all sections.
摘要:
The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.