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    NAND flash memory systems with efficient soft information interface
    3.
    发明授权
    NAND flash memory systems with efficient soft information interface 有权
    NAND闪存系统具有高效的软信息接口

    公开(公告)号：US09467170B2

    公开(公告)日：2016-10-11

    申请号：US14267307

    申请日：2014-05-01

    申请人： Marvell World Trade LTD.

    发明人： Shashi Kiran Chilappagari ,  Gregory Burd

    IPC分类号： H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H03M13/39 ,  G11C29/52 ,  G06F11/10 ,  H03M13/00

    CPC分类号： H03M13/1111 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/2927 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3707 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/3927 ,  H03M13/41 ,  H03M13/45 ,  H03M13/458 ,  H03M13/6513

    摘要： A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword.

    摘要翻译： 非易失性存储器件的控制器包括转移控制模块和解码器模块。 转移控制模块被配置为请求从闪存模块读取数据。 要读取的数据包括对应于第一码字的数据。 传送控制模块被配置为从闪存模块接收对应于第一码字的硬判决。 传送控制模块被配置为从闪存模块接收对应于第一码字的软信息。 接收对应于第一码字的硬判决和对应于第一码字的软信息，而不接收与另一码字对应的任何介入的硬判决或软信息。 解码器模块被配置为使用硬判决和对应于第一码字的软信息来解码第一码字。

    System and method for random noise generation
    5.
    发明授权
    System and method for random noise generation 有权
    随机噪声产生的系统和方法

    公开(公告)号：US09235488B2

    公开(公告)日：2016-01-12

    申请号：US14168222

    申请日：2014-01-30

    申请人： PMC-SIERRA US, INC.

    发明人： Christopher I. W. Norrie

    IPC分类号： G06F11/22 ,  H03M13/39 ,  H03M13/11 ,  G06F11/10

    CPC分类号： G06F11/2215 ,  G06F11/1012 ,  H03M13/1111 ,  H03M13/3905 ,  H03M13/3927

    摘要： A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.

    摘要翻译： 一种随机噪声生成模块，用于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。 所述随机噪声生成模块包括用于产生一个或多个系数的系数发生器，所述多个系数中的每一个与多个区域中的一个区域相关联，所述多个区域定义根据在概率分布曲线下的区域成比例地划分的线性空间 非易失性存储器存储模块。 随机噪声生成模块还包括用于生成线性随机数的线性随机数发生器和用于将线性随机数与多个系数中的一个或多个进行比较的比较器，以识别概率分布曲线的多个区域的区域 其中线性随机数属于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。

    MAX-LOG-MAP EQUIVALENCE LOG LIKELIHOOD RATIO GENERATION SOFT VITERBI ARCHITECTURE SYSTEM AND METHOD
    8.
    发明申请
    MAX-LOG-MAP EQUIVALENCE LOG LIKELIHOOD RATIO GENERATION SOFT VITERBI ARCHITECTURE SYSTEM AND METHOD 审中-公开
    最大日志映射等效日志比例生成软件VITERBI架构系统和方法

    公开(公告)号：US20140240863A1

    公开(公告)日：2014-08-28

    申请号：US14192674

    申请日：2014-02-27

    申请人： STMICROELECTRONICS INC.

    发明人： Sivagnanam PARTHASARATHY ,  Lun Bin HUANG ,  Alessandro RISSO

    IPC分类号： H03M13/41 ,  G11B20/18 ,  G06F11/10

    CPC分类号： H03M13/4146 ,  G06F11/1076 ,  G11B20/18 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/4184 ,  H03M13/42 ,  H03M13/6343 ,  H03M13/6502 ,  H04L1/0054 ,  H04L1/0055

    摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

    摘要翻译： 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。

    Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
    9.
    发明授权
    Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method 有权
    最大对数映射等价对数似然比生成软维特比架构系统和方法

    公开(公告)号：US08694877B2

    公开(公告)日：2014-04-08

    申请号：US12924707

    申请日：2010-10-01

    申请人： Sivagnanam Parthasarathy ,  Lun Bin Huang ,  Alessandro Risso

    发明人： Sivagnanam Parthasarathy ,  Lun Bin Huang ,  Alessandro Risso

    IPC分类号： H03M13/03

    CPC分类号： H03M13/4146 ,  G06F11/1076 ,  G11B20/18 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/4184 ,  H03M13/42 ,  H03M13/6343 ,  H03M13/6502 ,  H04L1/0054 ,  H04L1/0055

    摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

    摘要翻译： 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。