公开(公告)号：US07861146B2

公开(公告)日：2010-12-28

申请号：US11597541

申请日：2005-02-16

申请人： Kouya Watanabe ,  Takehiro Kamada

发明人： Kouya Watanabe ,  Takehiro Kamada

IPC分类号： H03M13/41

CPC分类号： H03M13/3994 ,  H03M13/4176

摘要： In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (106). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.

摘要翻译： 在维特比解码装置中，控制终止码之前和之后的纠错能力的恶化。 终端定时检测单元（103）检测维特比码的终止定时，强制生成单元（105）产生强制值，以便在终止定时和终止定时之前和之后的定时通过特定路径，并且 强制值设置在回溯指针（106）上。 因此，即使当终止之前的代码的解码状态劣化时，也可以不影响劣化地执行下一个代码的解码，从而提高纠错能力。

公开(公告)号：US08762822B2

公开(公告)日：2014-06-24

申请号：US13351613

申请日：2012-01-17

申请人： Richard A. Lane ,  Mark B. Murphy ,  Cyril Valadon ,  Francesc Boixadera

发明人： Richard A. Lane ,  Mark B. Murphy ,  Cyril Valadon ,  Francesc Boixadera

IPC分类号： H03M13/03

CPC分类号： H03M13/413 ,  H03M13/4169 ,  H03M13/4176 ,  H03M13/451

摘要： Techniques are provided for decoding tail-biting convolutional codes by using information within the received data stream that traditionally has not been used or been available to the convolutional decoder, e.g., cyclic redundancy check (CRC) and bit information known by both the transmitter and receiver. Further, a single parallel trace-back is used that reduces implementation complexity. In addition, the least reliable decisions made during forward processing may be reversed in order to generate additional possible codeword candidates. These techniques can be used to reduce false detection rates (FDRs) and/or detection error rates (DERs).

摘要翻译： 提供了通过使用传统上没有被使用或可用于卷积解码器的接收数据流中的信息来解码尾部卷积码的技术，例如循环冗余校验（CRC）和由发射机和接收机已知的比特信息 。 此外，使用单个并行跟踪来降低实现复杂度。 另外，为了生成额外的可能的码字候选，在正向处理期间做出的最不可靠的决定可以颠倒。 这些技术可用于降低错误检测率（FDR）和/或检测错误率（DER）。

公开(公告)号：US20130216006A1

公开(公告)日：2013-08-22

申请号：US13847208

申请日：2013-03-19

申请人： RESEARCH IN MOTION LIMITED

发明人： Martin KOSAKOWSKI

IPC分类号： H04L1/00

CPC分类号： H04L1/006 ,  H03M13/413 ,  H03M13/4169 ,  H03M13/4176 ,  H04L1/0054 ,  H04L1/0061

摘要： In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.

摘要翻译： 在各个方面，本公开描述了用于解码卷积编码信号的系统和方法，该信号表示例如电信信号，例如在数字电信中使用的命令或内容信号。 在各种实施例中，本公开的这些方面提供了用于通过提供用于并行处理编码数据记录的各个部分的架构和方法来提高这些过程的效率，速度和功耗的系统和方法，其使用多个和任选地特别设计的， 专用存储器寄存器和多路复用器。

公开(公告)号：US20060129903A1

公开(公告)日：2006-06-15

申请号：US11118175

申请日：2005-04-29

申请人： Yun-I Shih ,  Hsien-Yuan Hsu ,  Hung-Jua Ting ,  Chun-Hao Huang

发明人： Yun-I Shih ,  Hsien-Yuan Hsu ,  Hung-Jua Ting ,  Chun-Hao Huang

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/3738 ,  H03M13/4176 ,  H03M13/4192

摘要： A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the traceback modules when making a successful prediction. In other words, no access to the path memories is required. The predicted bits decoded and outputted by the decode bit registers are the decoded bits from the Viterbi decoder. Therefore, the prediction device saves much traceback works and power consumption for decoding.

摘要翻译： 提供了一种用于维特比解码器的预测装置和方法。 预测装置适用于具有低误码率的通信系统，用于减少访问路径存储器的计数，从而降低系统的功耗。 预测设备在进行成功预测时，不需要激活追溯模块。 换句话说，不需要访问路径存储器。 由解码位寄存器解码和输出的预测位是来自维特比解码器的解码位。 因此，预测装置可以节省大量的追溯功能和解码功耗。

公开(公告)号：US5907586A

公开(公告)日：1999-05-25

申请号：US704475

申请日：1996-08-27

申请人： Hiroshi Katsuragawa ,  Shigeru Ono

发明人： Hiroshi Katsuragawa ,  Shigeru Ono

IPC分类号： H04L27/00 ,  H03M13/01 ,  H03M13/09 ,  H03M13/23 ,  H03M13/41 ,  H04J13/00 ,  H04L1/00 ,  H04L1/08 ,  H04L1/20 ,  H03D1/00 ,  G06F11/10 ,  H04B7/216 ,  H04L23/02

CPC分类号： H04L1/08 ,  H03M13/3955 ,  H03M13/4107 ,  H03M13/4146 ,  H03M13/4176 ,  H03M13/6337 ,  H03M13/6502 ,  H04L1/0046 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/0061 ,  H03M13/3776

摘要： A method and a device for signal decision, a receiver and a channel condition estimating method for a coding communication system are disclosed. A plurality of add, compare and select (ACS) circuits each sequentially determines metrics at a particular trellis tracing rate assigned thereto. The metrics are sequentially added in order to select the most probable path. An M break-up circuit 30 compares the path metrics of the most probable paths and breaks up unlikely paths over a plurality of circuits. The path metrics of probable paths are sequentially written to respective metric memories and again fed to the ACS circuits for trellis tracings. This is repeated until the M break-up circuit 30 selects M paths out of paths fed from N (N>M) ACS circuits. The M paths are delivered to a decision circuit while survivor paths are written to respective path memories. The decision circuit selects one of the M path metrics having the smallest value, reads the path out of the path memory, traces it back, and then outputs decoded bits via an output terminal.

摘要翻译： 公开了用于信号判定的方法和装置，用于编码通信系统的接收机和信道条件估计方法。 多个添加，比较和选择（ACS）电路每个顺序地以指定给它的特定网格跟踪速率确定度量。 为了选择最可能的路径，顺序添加度量。 M分解电路30比较最可能路径的路径度量并且在多个电路上分解不太可能的路径。 可能路径的路径度量被顺序地写入相应的度量存储器，并再次馈送到用于格状跟踪的ACS电路。 重复这一步骤直到M断路电路30从N（N> M）个ACS电路馈送的路径中选出M个路径。 M路径被传送到决定电路，而幸存路径被写入相应的路径存储器。 决定电路选择具有最小值的M路径量度中的一个，读取路径存储器中的路径，追踪它，然后经由输出端输出解码位。

公开(公告)号：US08904266B2

公开(公告)日：2014-12-02

申请号：US12853589

申请日：2010-08-10

申请人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergie Valerjewitsch Sawitzki

发明人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergie Valerjewitsch Sawitzki

IPC分类号： H03M13/17 ,  H03M13/00 ,  H03M13/41

CPC分类号： H03M13/4176 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

摘要翻译： 各种实施例涉及多标准维特比解码器。 基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。 在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。 各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。 在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

公开(公告)号：US08433004B2

公开(公告)日：2013-04-30

申请号：US12713502

申请日：2010-02-26

申请人： Martin Kosakowski

发明人： Martin Kosakowski

IPC分类号： H04L27/06

CPC分类号： H04L1/006 ,  H03M13/413 ,  H03M13/4169 ,  H03M13/4176 ,  H04L1/0054 ,  H04L1/0061

摘要： In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.

摘要翻译： 在各个方面，本公开描述了用于解码卷积编码信号的系统和方法，该信号表示例如电信信号，例如在数字电信中使用的命令或内容信号。 在各种实施例中，本公开的这些方面提供了用于通过提供用于并行处理编码数据记录的各个部分的架构和方法来提高这些过程的效率，速度和功耗的系统和方法，其使用多个和任选地特别设计的， 专用存储器寄存器和多路复用器。

公开(公告)号：US20070234190A1

公开(公告)日：2007-10-04

申请号：US11597541

申请日：2005-02-16

申请人： Kouya Watanabe ,  Takehiro Kamada

发明人： Kouya Watanabe ,  Takehiro Kamada

IPC分类号： H03M13/41

CPC分类号： H03M13/3994 ,  H03M13/4176

摘要： In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (106). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.

摘要翻译： 在维特比解码装置中，控制终止码之前和之后的纠错能力的恶化。 终端定时检测单元（103）检测维特比码的终止定时，强制生成单元（105）产生强制值，以便在终止定时和终止定时之前和之后的定时通过特定路径，并且 强制值设置在回溯指针（106）上。 因此，即使当终止之前的代码的解码状态劣化时，也可以不影响劣化地执行下一个代码的解码，从而提高纠错能力。

公开(公告)号：US20070104296A1

公开(公告)日：2007-05-10

申请号：US11473126

申请日：2006-06-23

申请人： Toshiyuki Miyauchi ,  Yuichi Mizutani

发明人： Toshiyuki Miyauchi ,  Yuichi Mizutani

IPC分类号： H03D1/00 ,  H03M13/03

CPC分类号： H03M13/4176 ,  H03M13/4169 ,  H03M13/6502

摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.

摘要翻译： 本发明可以减少跟踪时的功耗。 本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元 其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元， 路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域 对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域 在各个时间点读取数据，以停止从指定的子区域读取数据。

公开(公告)号：US06748034B2

公开(公告)日：2004-06-08

申请号：US09215452

申请日：1998-12-17

申请人： Masayuki Hattori ,  Toshiyuki Miyauchi

发明人： Masayuki Hattori ,  Toshiyuki Miyauchi

IPC分类号： H04L2706

CPC分类号： H03M13/6583 ,  H03M13/4107 ,  H03M13/4123 ,  H03M13/4161 ,  H03M13/4176

摘要： A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register (1021) in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.

摘要翻译： 除了与每个状态相对应地布置有与切割长度一样多的存储单元串之外，还提供了一个寄存器列。 对应于状态00的寄存器列中的各个级的选择器的输出被输入到寄存器列和选择器中的寄存器（1021）。 前级寄存器的输出分别输入到这三个选择器。 当接收字终止时，根据控制电路的控制，在其他情况下，三个选择器将输出切换到后级。 因此，当接收字终止时，存储在寄存器列中的信息被原样传送。 通过这样的操作，当接收字终止时，可以对达到状态00的路径进行解码。