公开(公告)号：US20120023383A1

公开(公告)日：2012-01-26

申请号：US13157042

申请日：2011-06-09

申请人： Takashi MAEHATA

发明人： Takashi MAEHATA

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1145 ,  H03M13/1111 ,  H03M13/1134 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/616 ,  H03M13/6563 ,  H04L1/0057

摘要： A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.

摘要翻译： 解码器5并行地对N个输入数据进行解码处理，生成K个解码数据。 S / P转换器6通过分割数次的第一线L1-L64输出对解码器5串联施加的N个输入数据。 P / S转换器7通过第二线路R1-R60从解码器5接收数次的K个解码数据，将K个解码的数据串行输出到外部源。

公开(公告)号：US07409606B2

公开(公告)日：2008-08-05

申请号：US11216867

申请日：2005-08-31

申请人： Noriyuki Nakai

发明人： Noriyuki Nakai

IPC分类号： H03M13/27

CPC分类号： H03M13/2957 ,  H03M13/2771 ,  H03M13/3905 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/6563

摘要： A method and system for interleaving in a parallel turbo decoder enables the use of economical dual-port memory. According to the method, an incoming coding block is divided into a plurality of sub-blocks (step 1005). Each sub-block is divided into a plurality of windows (step 1010). An inter-window shuffle is then performed within each sub-block (step 1015). Each window is divided into two sub-windows (step 1020). Then an intra-window permutation is performed within each sub-window (step 1025).

摘要翻译： 并行turbo解码器中的交织方法和系统使得能够使用经济的双端口存储器。 根据该方法，将输入编码块划分为多个子块（步骤1005）。 每个子块被分成多个窗口（步骤1010）。 然后在每个子块内执行窗间随机播放（步骤1015）。 每个窗口被分成两个子窗口（步骤1020）。 然后在每个子窗口内执行窗口内排列（步骤1025）。

公开(公告)号：US20050163233A1

公开(公告)日：2005-07-28

申请号：US11022811

申请日：2004-12-28

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

IPC分类号： G06F11/10 ,  H03M13/23 ,  H03M13/41 ,  H04L1/00 ,  H04B14/04

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.

摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。

公开(公告)号：US06484283B2

公开(公告)日：2002-11-19

申请号：US09223473

申请日：1998-12-30

申请人： Karen J. Stephen ,  Hon W. Lam ,  Jonathan Cromwell

发明人： Karen J. Stephen ,  Hon W. Lam ,  Jonathan Cromwell

IPC分类号： H03M1303

CPC分类号： H04L1/005 ,  H03M13/258 ,  H03M13/2746 ,  H03M13/2957 ,  H03M13/333 ,  H03M13/3911 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3972 ,  H03M13/3988 ,  H03M13/6563 ,  H04L1/0043 ,  H04L1/0052 ,  H04L1/0066

摘要： The present invention is a method and apparatus for encoding and decoding a turbo code. In the encoder, an interleaver interleaves and delays a block of input bits to generate interleaved input bits and delayed input bits. A first encoder generates a first, second, and third encoded bits. A second encoder generates a fourth encoded bit. A symbol generator generates a plurality of symbols which correspond to the input bits. In a decoder, a sync search engine detects a synchronizing pattern and extracts symbols from the encoded bits. An input buffer is coupled to the sync search engine to store the extracted symbols. A first soft-in-soft-out (SISO1) is coupled to the input buffer to generate a first soft decision set based on the extracted symbols. An interleaver is coupled to the SISO1 to interleave the first soft decision set. A second soft-in-soft-out (SISO2) is coupled to the input buffer and the interleaver to generate a second soft decision set. A de-interleaver is coupled to the SISO2 to de-interleave the second soft decision set. An adder is coupled to the SISO1 and the de-interleaver to generate a hard decision set.

摘要翻译： 本发明是用于对turbo码进行编码和解码的方法和装置。 在编码器中，交织器交织并延迟输入比特块以产生交织的输入比特和延迟的输入比特。 第一编码器生成第一，第二和第三编码比特。 第二编码器生成第四编码位。 符号发生器产生对应于输入比特的多个符号。 在解码器中，同步搜索引擎检测同步模式并从编码比特中提取符号。 输入缓冲器耦合到同步搜索引擎以存储所提取的符号。 第一软进软输出（SISO1）耦合到输入缓冲器以基于提取的符号生成第一软判决集。 交织器耦合到SISO1以交织第一软判决集。 第二软入软件（SISO2）耦合到输入缓冲器和交织器以产生第二软判决集。 解交织器耦合到SISO2以对第二软判决集进行解交织。 加法器耦合到SISO1和解交织器以产生硬判决集。

公开(公告)号：US06477661B2

公开(公告)日：2002-11-05

申请号：US09974807

申请日：2001-10-12

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

IPC分类号： G06F1100

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。

公开(公告)号：US06448910B1

公开(公告)日：2002-09-10

申请号：US09818746

申请日：2001-03-26

申请人： Guangming Lu

发明人： Guangming Lu

IPC分类号： H03M738

CPC分类号： H03M13/6511 ,  H03M13/23 ,  H03M13/3961 ,  H03M13/4169 ,  H03M13/6563

摘要： A method and apparatus for convolution encoding and Viterbi decoding utilizes a flexible, digital signal processing architecture that comprises a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array. The core processor is operable to configure the re-configurable processing elements to perform data encoding and data decoding functions. A received data input is encoded by configuring one of the re-configurable processing elements to emulate a convolution encoding algorithm and applying the received data input to the convolution encoding algorithm. A received encoded data input is decoded by configuring the plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm wherein the plurality of re-configurable processing elements is configured to accommodate every data state of the convolution encoding algorithm. The core processor initializes the re-configurable processing elements by assigning register values to registers that define parameters such as constraint length and code rate for the convolution encoding algorithm.

摘要翻译： 用于卷积编码和维特比解码的方法和装置利用灵活的数字信号处理架构，其包括核心处理器和以二维阵列布置的多个可重新配置的处理元件。 核心处理器可操作地配置可重新配置的处理元件以执行数据编码和数据解码功能。 通过配置可重新配置的处理元件之一来对接收的数据输入进行编码，以模拟卷积编码算法并将接收到的数据输入应用于卷积编码算法。 接收的编码数据输入被解码，通过配置多个可重新配置的处理元件来模拟维特比解码算法，其中多个可重新配置的处理元件被配置为适应卷积编码算法的每个数据状态。 核心处理器通过为定义诸如卷积编码算法的约束长度和码率等参数的寄存器分配寄存器值来初始化可重新配置的处理元件。

公开(公告)号：US20160142075A1

公开(公告)日：2016-05-19

申请号：US14940091

申请日：2015-11-12

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Takashi MAEHATA

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1145 ,  H03M13/1111 ,  H03M13/1134 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/616 ,  H03M13/6563 ,  H04L1/0057

摘要： A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.

公开(公告)号：US20160056843A1

公开(公告)日：2016-02-25

申请号：US14930879

申请日：2015-11-03

申请人： Warren Gross ,  Gabi Sarkis

发明人： Warren Gross ,  Gabi Sarkis

IPC分类号： H03M13/39 ,  H03M13/00 ,  G06F17/16 ,  G06F17/14 ,  H03M13/15 ,  G06F17/30

CPC分类号： H03M13/3927 ,  G06F17/10 ,  G06F17/142 ,  G06F17/16 ,  G06F17/30958 ,  G06F17/30961 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/13 ,  H03M13/157 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6577

摘要： Coding within noisy communications channels is essential but a theoretical maximum rate defines the rate at which information can be reliably transmitted on this noisy channel. Capacity-achieving codes with an explicit construction eluded researchers until polar codes were proposed. However, whilst asymptotically reaching channel capacity these require increasing code lengths, and hence increasingly complex hardware implementations. It would be beneficial to address architectures and decoding processes to reduce polar code decoder complexity both in terms of the number of processing elements required, but also the number of memory elements and the number of steps required to decode a codeword. Beneficially architectures and design methodologies established by the inventors address such issues whilst reducing overall complexity as well as providing methodologies for adjusting decoder design based upon requirements including, but not limited to, cost (e.g. through die area) and speed (e.g. through latency, number of cycles, number of elements etc).

摘要翻译： 噪声通信信道中的编码是必不可少的，但是理论上的最大速率定义了在这个噪声信道上可靠地发送信息的速率。 在提出极性代码之前，具有明确结构的能力实现代码不包括研究人员。 然而，虽然渐近地达到信道容量，但这些需要增加代码长度，并因此增加复杂的硬件实现。 解决架构和解码过程将有利于在所需的处理元件的数量方面降低极性码解码器的复杂性，而且还要解码码字所需的存储器元件的数量和步骤的数量。 本发明人建立的有利的架构和设计方法解决了这样的问题，同时降低了整体的复杂性，并且提供了基于需求来调整解码器设计的方法，包括但不限于成本（例如，通过管芯面积）和速度（例如通过延迟，数量 周期数，元素数等）。

公开(公告)号：US20140019821A1

公开(公告)日：2014-01-16

申请号：US14028241

申请日：2013-09-16

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Takashi MAEHATA

IPC分类号： H04L1/00

CPC分类号： H03M13/1145 ,  H03M13/1111 ,  H03M13/1134 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/616 ,  H03M13/6563 ,  H04L1/0057

摘要： A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.

摘要翻译： 解码器5并行地对N个输入数据进行解码处理，生成K个解码数据。 S / P转换器6通过分割数次的第一线L1-L64输出对解码器5串联施加的N个输入数据。 P / S转换器7通过第二线路R1-R60从解码器5接收数次的K个解码数据，将K个解码的数据串行输出到外部源。

公开(公告)号：US08572453B2

公开(公告)日：2013-10-29

申请号：US13157042

申请日：2011-06-09

申请人： Takashi Maehata

发明人： Takashi Maehata

IPC分类号： H03M13/00

CPC分类号： H03M13/1145 ,  H03M13/1111 ,  H03M13/1134 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/616 ,  H03M13/6563 ,  H04L1/0057

摘要： A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.