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公开(公告)号：US09571927B2
公开(公告)日：2017-02-14
申请号：US14437685
申请日：2013-10-10
发明人： John Paul Lesso
摘要： This application relates to digital-to-analogue conversion with improved noise performance. Embodiments relate to digital-to-analogue conversion circuits (300) for converting a digital audio signal to an analogue audio signal having a digital-to-analogue converter (104) operable at a plurality of DAC clock rates. A first clock controller (301-1) controls the DAC clock rate based on an indication of the amplitude of the audio signal. The DAC clock rate (CK1) may be increased for low amplitude signal, where noise is important, to reduce the in-band thermal noise of the DAC. At higher amplitudes, when noise is less audible, the DAC clock rate may be reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector (302) or in some cases by an analogue level detector (303). The DAC may be an oversampling DAC with an input interpolator (101) The conversion circuit may also include a word-length reduction module (102) and a dynamic error matching module (103) whose clock rates may also be varied based on the signal.
摘要翻译： 该应用涉及具有改进的噪声性能的数模转换。 实施例涉及用于将数字音频信号转换为模拟音频信号的数模转换电路（300），模拟音频信号具有可以多个DAC时钟速率工作的数模转换器（104）。 第一时钟控制器（301-1）基于音频信号的幅度的指示来控制DAC时钟速率。 对于噪声很重要的低幅度信号，DAC时钟频率（CK1）可能会增加，以降低DAC的带内热噪声。 在较高的幅度下，当噪声较小时，DAC时钟频率可能会降低，以避免失真。 音频信号的幅度可以由数字电平检测器（302）监视，或者在某些情况下由模拟电平检测器（303）监视。 DAC可以是具有输入内插器的过采样DAC（101）。转换电路还可以包括字长减小模块（102）和动态误差匹配模块（103），其时钟速率也可以基于该信号而变化。
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公开(公告)号：US08570201B2
公开(公告)日：2013-10-29
申请号：US13354337
申请日：2012-01-20
IPC分类号： H03M3/02
摘要： A continuous-time sigma-delta analog-to-digital converter includes a plurality of integrator stages, in which one of the integrator stages includes a current buffer that drives an integrating capacitor. The analog-to-digital converter includes an outer feedback digital-to-analog converter and an inner digital-to-analog converter. The inner digital-to-analog converter is a current-mode digital-to-analog converter that converts the digital output signal to an analog current feedback signal, which is provided to an output of the integrator stage that includes the current buffer. Both the analog current feedback signal and an input signal provided to the current buffer are integrated by the integrating capacitor.
摘要翻译： 连续时间Σ-Δ模数转换器包括多个积分器级，其中一个积分器级包括驱动积分电容器的电流缓冲器。 模数转换器包括外部反馈数模转换器和内部数模转换器。 内部数模转换器是电流模式数模转换器，其将数字输出信号转换为模拟电流反馈信号，该信号被提供给包括当前缓冲器的积分器级的输出端。 模拟电流反馈信号和提供给当前缓冲器的输入信号都由积分电容器积分。
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公开(公告)号：US20130021184A1
公开(公告)日：2013-01-24
申请号：US13354337
申请日：2012-01-20
IPC分类号： H03M3/02
摘要： A continuous-time sigma-delta analog-to-digital converter includes a plurality of integrator stages, in which one of the integrator stages includes a current buffer that drives an integrating capacitor. The analog-to-digital converter includes an outer feedback digital-to-analog converter and an inner digital-to-analog converter. The inner digital-to-analog converter is a current-mode digital-to-analog converter that converts the digital output signal to an analog current feedback signal, which is provided to an output of the integrator stage that includes the current buffer. Both the analog current feedback signal and an input signal provided to the current buffer are integrated by the integrating capacitor.
摘要翻译： 连续时间Σ-Δ模数转换器包括多个积分器级，其中一个积分器级包括驱动积分电容器的电流缓冲器。 模数转换器包括外部反馈数模转换器和内部数模转换器。 内部数模转换器是电流模式数模转换器，其将数字输出信号转换为模拟电流反馈信号，该信号被提供给包括当前缓冲器的积分器级的输出端。 模拟电流反馈信号和提供给当前缓冲器的输入信号都由积分电容器积分。
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4.发明授权Continuous-time sigma-delta modulator with multiple feedback paths having independent delays 有权具有多个具有独立延迟的反馈路径的连续时间Σ-Δ调制器公开(公告)号：US07880654B2
公开(公告)日：2011-02-01
申请号：US12394275
申请日：2009-02-27
申请人： Omid Oliaei , Brandt Braswell
发明人： Omid Oliaei , Brandt Braswell
IPC分类号： H03M3/00
摘要： Apparatus are provided for continuous-time sigma-delta modulators. A sigma-delta modulator comprises a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer, and the main feedback arrangement delays the digital value by a first delay period and generates a main feedback signal based on the delayed value. A compensation feedback arrangement is coupled to the quantizer, and compensation feedback arrangement delays the digital value by a second delay period and generates a compensation feedback signal based on the delayed value. A forward signal arrangement produces the analog signal at the quantizer based on an input signal, the main feedback signal, and the compensation feedback signal. The second delay period is independent of and is not influenced by the first delay period, and the second delay period is chosen such that the compensation feedback signal compensates for the first delay period.
摘要翻译： 提供了连续时间Σ-Δ调制器的装置。 Σ-Δ调制器包括被配置为将模拟信号转换为数字值的量化器。 主反馈装置耦合到量化器，并且主反馈装置将数字值延迟第一延迟周期，并且基于延迟值产生主反馈信号。 补偿反馈装置耦合到量化器，并且补偿反馈装置将数字值延迟第二延迟周期，并且基于延迟值产生补偿反馈信号。 正向信号装置基于输入信号，主反馈信号和补偿反馈信号在量化器处产生模拟信号。 第二延迟周期与第一延迟周期无关并且不受第一延迟周期的影响，并且选择第二延迟周期使得补偿反馈信号补偿第一延迟周期。
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公开(公告)号：US20050052299A1
公开(公告)日：2005-03-10
申请号：US10381075
申请日：2003-03-18
申请人： Omid Oliaei
发明人： Omid Oliaei
摘要： An analogue-to-digital sigma-delta modulator for converting analogue input signals to digital output signals comprises a feedback path (1, 101, 201) for producing analogue feedback signals that are a function of the digital output signals (y, Y), an ‘N’-stage (‘N’≧2) integrator path (9 to 14, 109 to 114) for integrating analogue difference signals that are a difference function of the input signal and the analogue feedback signals, and a quantizer (3, 103) responsive to the signals integrated by the integrator means (9 to 14, 109 to 114) for producing the digital output signals (y, Y) at clock intervals. The feedback path includes ‘N’ feedback stages (15 to 17, 115 to 117) for respective integrator stages (9 to 14, 109 to 114). Each of the ‘N’ feedback stages (15 to 17, 115 to 117) comprises finite impulse response (‘FIR’) filters (15 to 19, 115 to 117), each of the FIR filters being of the same order ‘M’, where ‘M’ is at least two; at least the filter (15, 115) of the feedback stage that feeds back to the first integrator stage is a low pass filter. The integrator stages may be discrete-time integrators; the FIR filters reduce their sensitivity to feedback voltage step changes that would cause non-linearities due to slew-rate limitations. Alternatively, the integrator stages may be continuous-time integrators; the FIR filters reduce their sensitivity to clock pulse jitters. In the embodiment shown in FIG. 11, the first integrator stage (109, 110) is a continuous-time integrator stage, and the remainder of the integrator stages (11 to 14) are discrete-time integrator stages.
摘要翻译： 一种用于将模拟输入信号转换为数字输出信号的模拟 - 数字Σ-Δ调制器包括用于产生作为数字输出信号（y，Y）的函数的模拟反馈信号的反馈路径（1,101,201） 用于对作为输入信号和模拟反馈信号的差分函数的模拟差分信号进行积分的“N”级（“N”= 2）积分器路径（9〜14,109〜114），以及量化器 ，103）响应于由积分器装置（9至14,109至114）积分的信号，用于以时钟间隔产生数字输出信号（y，Y）。 反馈路径包括用于各积分器级（9〜14,109〜114）的“N”个反馈级（15〜17,115〜117）。 “N”个反馈级（15〜17,115〜117）中的每一个包括有限脉冲响应（“FIR”）滤波器（15〜19,115〜117），每个FIR滤波器具有相同的阶数“M” ，其中'M'至少为2; 至少反馈到第一积分器级的反馈级的滤波器（15,115）是低通滤波器。 积分器级可以是离散时间积分器; FIR滤波器降低了对由于压摆率限制导致非线性的反馈电压阶跃变化的敏感性。 或者，积分器级可以是连续时间积分器; FIR滤波器可以降低对时钟脉冲抖动的敏感度。 在
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公开(公告)号：US07768433B2
公开(公告)日：2010-08-03
申请号：US12173006
申请日：2008-07-14
申请人： Lennart K-A Mathe , Xiaohong Quan
发明人： Lennart K-A Mathe , Xiaohong Quan
IPC分类号： H03M3/00
CPC分类号： H03M3/374 , H03K17/567 , H03K17/687 , H03M3/424 , H03M3/452
摘要： Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ΔΣ ADC) are described. In one design, a ΔΣ ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ΔΣ ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled.
摘要翻译： 描述了用于增强反馈电路（例如，＆amp; ADC）内的有源电路的转换速率的技术。 在一个设计中，一个＆D＆ ADC包括积分器，转换速率增强电路和控制电路。 积分器接收输入信号并提供输出信号。 转换速率增强电路基于＆Dgr＆amp; Sgr中的反馈信号增强积分器的转换速率。 ADC。 转换速率增强电路可以仅提供反馈信号的某些值（例如，最大值和最小值）的升压电流，或者（ii）反馈信号的不同值的不同的升压电流量。 在一种设计中，转换速率增强电路包括耦合到积分器的至少一个升压电路。 当升压电路使能时，每个升压电路都提供升压电流，以提高积分器的转换速率。
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公开(公告)号：US07580452B2
公开(公告)日：2009-08-25
申请号：US11281311
申请日：2005-11-17
申请人： Benny Wing Hung Lai
发明人： Benny Wing Hung Lai
IPC分类号： H03K5/159
摘要： A dynamic comparator system includes a dynamic comparator, a feedback filter, and a summer. The dynamic comparator is configured with a comparison signal having an initial state. The dynamic comparator is further configured to receive an input signal and to generate an output signal. The feedback filter is configured to receive the output signal from the dynamic comparator and to generate a filter response signal therefrom. The summer is configured to receive the filter response signal from the feedback filter, to receive the input signal, and to generate a sum signal combining the filter response signal and the input signal. The dynamic comparator compares the input signal to the initial state of the comparison signal, and based on the comparison, optionally adjusts the state of the comparison signal.
摘要翻译： 动态比较器系统包括动态比较器，反馈滤波器和夏季。 动态比较器配置有具有初始状态的比较信号。 动态比较器还被配置为接收输入信号并产生输出信号。 反馈滤波器被配置为从动态比较器接收输出信号并从其产生滤波器响应信号。 夏天被配置为从反馈滤波器接收滤波器响应信号，以接收输入信号，并且产生组合滤波器响应信号和输入信号的和信号。 动态比较器将输入信号与比较信号的初始状态进行比较，并且基于比较，可选地调整比较信号的状态。
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公开(公告)号：US06836228B1
公开(公告)日：2004-12-28
申请号：US10301129
申请日：2002-11-20
申请人： Roger Levinson , Phillip J. Benzel
发明人： Roger Levinson , Phillip J. Benzel
IPC分类号： H03M100
摘要： Methods and apparatus for converting analog signals to digital signals using a switched integrator. A method includes receiving the analog signal at a summing junction, receiving a clock signal transitioning between a first level and a second level, connecting an output of the summing junction to an integrator when the clock signal is at the first level, and disconnecting the output of the summing junction from the integrator when the clock signal is at the second level. An output signal is provided, and is determined by the polarity of an output of the integrator when the clock signal transitions from the first level to the second level. The output signal is delayed, and received with a digital-to-analog converter; which provides an output to the summing junction.
摘要翻译： 使用开关积分器将模拟信号转换为数字信号的方法和装置。 一种方法包括在加法结处接收模拟信号，接收在第一电平和第二电平之间转换的时钟信号，当时钟信号处于第一电平时将求和结点的输出连接到积分器，以及断开输出 当时钟信号处于第二电平时，来自积分器的求和结点。 提供输出信号，并且当时钟信号从第一电平转变到第二电平时由积分器的输出的极性确定。 输出信号被延迟，并用数/模转换器接收; 其向求和结点提供输出。
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9.发明授权High-order delta sigma analog-to-digital converter with unit-delay integrators 失效具有单位延迟积分器的高阶Δ西格玛模数转换器
公开(公告)号：US5682160A
公开(公告)日：1997-10-28
申请号：US650282
申请日：1996-05-20
摘要： A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.
摘要翻译： 一个ΔΣ调制器使得每个级联积分器能够在一个完整的时钟周期内独立地稳定，并且使用反馈路径中的二项式系数来获得所需的量化器误差的正弦整形，实现了采样率和阶数的提高以提高分辨率。 使用多位量化器也可以提高调制器分辨率。 在一个实施例中，调制器包括多个级联的单位延迟积分器，并在反馈回路中利用二项式系数缩放。 多位模数转换器被耦合以接收级联单元延迟积分器的输出信号。 反馈回路包括耦合到多位模数转换器的输出的多位数模转换器。 数模转换器的输出耦合到至少第一和第二差分求和结的输入端。
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公开(公告)号：US5572107A
公开(公告)日：1996-11-05
申请号：US297625
申请日：1994-08-29
申请人： Rudolf Koch , Michael Alger-Meunier
发明人： Rudolf Koch , Michael Alger-Meunier
CPC分类号： H03H19/004 , H03M3/374 , H03M3/43 , H03M3/438
摘要： A switched capacitor network includes a first capacitor being charged and discharged in alternation by a first switch device and being connected to a first voltage source for charging. A second capacitor is charged and discharged by the second switch device in synchronism with the first capacitor and is switched between the first voltage source and the second voltage source for charging. A product of the capacitance of the first capacitor and the voltage of the first voltage source is equal to a product of the capacitance of the second capacitor and a voltage difference between the two voltage sources. A product of the capacitance of the first capacitor and a contact resistance of the first switch device in a supply line path thereof, is equal to a product of the capacitance of the second capacitor and a sum of an internal resistance of the second voltage source and a contact resistance of the second switch device in a supply line path of the second capacitor.
摘要翻译： 开关电容器网络包括由第一开关装置交替地充电和放电的第一电容器，并连接到用于充电的第一电压源。 第二电容器与第一电容器同步地由第二开关器件充电和放电，并且在第一电压源和第二电压源之间切换用于充电。 第一电容器的电容和第一电压源的电压的乘积等于第二电容器的电容和两个电压源之间的电压差的乘积。 第一电容器的电容和第一开关器件的电源线路径中的接触电阻的乘积等于第二电容器的电容与第二电压源的内部电阻和 第二开关器件在第二电容器的供电线路径中的接触电阻。
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