公开(公告)号：US20180309458A1

公开(公告)日：2018-10-25

申请号：US15912128

申请日：2018-03-05

申请人： Abhishek Bandyopadhyay ,  Rong Jin

发明人： Abhishek Bandyopadhyay ,  Rong Jin

IPC分类号： H03M1/08

CPC分类号： H03M1/0854 ,  H03M1/468 ,  H03M1/804 ,  H03M3/46

摘要： Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for efficient noise-shaping, e.g., in a noise-shaping feedback configuration. A preamplifier portion of a comparator circuit in an oversampling ADC can be re-purposed to provide an amplifier to amplify or otherwise modify a residue left after the bit trials of a conversion cycle. The amplified or modified residue can then be used elsewhere, for example, for noise-shaping by applying a noise transfer function (NTF), a result of which can then be fed back (e.g., summed with the next sampled input at an input of the comparator circuit for use in the N bit trials of the next ADC cycle).

公开(公告)号：US20180069564A1

公开(公告)日：2018-03-08

申请号：US15684285

申请日：2017-08-23

申请人： MEDIATEK INC.

发明人： Chun-Cheng LIU

IPC分类号： H03M1/08 ,  H03M1/00 ,  H03F3/00 ,  H03H17/02

CPC分类号： H03M1/08 ,  H03F3/005 ,  H03H17/0248 ,  H03M1/002 ,  H03M1/468 ,  H03M3/46

摘要： An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal.

公开(公告)号：US09742429B1

公开(公告)日：2017-08-22

申请号：US15095730

申请日：2016-04-11

申请人： Hypres, Inc.

发明人： Amol Inamdar ,  Deepnarayan Gupta

IPC分类号： H03M1/12 ,  H03M3/00 ,  H03M1/08

CPC分类号： H03M3/458 ,  H03M1/0854 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/68 ,  H03M3/02 ,  H03M3/46

摘要： Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

公开(公告)号：US09389252B2

公开(公告)日：2016-07-12

申请号：US14755850

申请日：2015-06-30

申请人： Semtech Corporation

发明人： Olivier Nys ,  Pascal Monney

IPC分类号： G01R13/14 ,  G01R19/25 ,  G01R19/10 ,  G01R19/252 ,  H03M3/00

CPC分类号： G01R19/25 ,  G01R19/10 ,  G01R19/252 ,  H03K2217/960735 ,  H03M3/414 ,  H03M3/46 ,  H03M3/466

摘要： A sampling circuitry for a plurality of electrodes the circuitry comprising a plurality of charge amplifiers and a plurality of modulators, wherein each charge amplifier and each modulator, comprised in the plurality of charge amplifiers and the plurality of modulators, respectively, corresponds to an electrode of the plurality of electrodes, wherein each modulator is capable of generating a residue signal and a rough code corresponding to each sampled electrode of the plurality of electrodes, a multiplexer capable of receiving a plurality of residue signals generated by the plurality of modulators, a residue analog to digital converter capable of receiving a multiplexed residue signal from the multiplexer and outputting a digitized multiplexed residue signal, and a digital summation circuitry capable of receiving the digitized multiplexed residue signal and a plurality of rough codes, comprising each rough code corresponding to each sample electrode, and outputting a plurality of output codes.

摘要翻译： 一种用于多个电极的采样电路，所述电路包括多个电荷放大器和多个调制器，其中分别包括在所述多个电荷放大器和所述多个调制器中的每个电荷放大器和每个调制器对应于 所述多个电极，其中每个调制器能够产生残留信号和对应于所述多个电极中的每个采样的电极的粗略码，多路复用器，其能够接收由所述多个调制器产生的多个残留信号;残差模拟 数字转换器，其能够从多路复用器接收多路复用的残留信号并输出​​数字化的多路复用残差信号;以及数字求和电路，其能够接收数字化多路复用残差信号和多个粗略码，包括对应于每个样本电极的每个粗略码 ，并输出多个outp ut代码。

公开(公告)号：US09276603B2

公开(公告)日：2016-03-01

申请号：US14852440

申请日：2015-09-11

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Yosuke Goto ,  Michiko Yamada

IPC分类号： H03M3/00

CPC分类号： H03M3/458 ,  H03M1/0695 ,  H03M1/14 ,  H03M1/144 ,  H03M3/46

摘要： An AD converter includes a delta-sigma AD converter configured to receive an analog signal through an input terminal and obtain a higher-order bit conversion result, a first cyclic AD converter configured to receive a residual signal resulting from removal of a higher-order bit or bits, and performs a conversion process having a amplification factor of one to obtain a 1.5-bit conversion result, a second cyclic AD converter configured to perform a conversion process having an amplification factor of two to obtain a lower-order bit conversion result, and a shift register and a digital accumulator circuit that are configured to receive a higher-order bit, a 1.5-bit, and a lower-order bit conversion result and output an AD conversion value.

摘要翻译： AD转换器包括被配置为通过输入端子接收模拟信号并获得高阶位转换结果的Δ-ΣAD转换器，第一循环AD转换器被配置为接收由去除高阶位产生的残留信号 或比特，并且执行具有放大因子1的转换处理以获得1.5位转换结果，第二循环AD转换器被配置为执行具有放大因子2的转换处理以获得低阶位转换结果， 以及移位寄存器和数字累加器电路，其配置为接收高位，1.5位和低位转换结果，并输出AD转换值。

公开(公告)号：US09236879B2

公开(公告)日：2016-01-12

申请号：US13985723

申请日：2012-02-17

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H03M1/12 ,  H03M1/18 ,  H04N5/378 ,  H03M1/16 ,  H03M1/40 ,  H03M1/56

CPC分类号： H03M1/18 ,  H03M1/162 ,  H03M1/403 ,  H03M1/56 ,  H03M3/39 ,  H03M3/46 ,  H04N5/378

摘要： According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration.

摘要翻译： 根据该A / D转换器，通过在相同的电路配置中的操作程序的控制来实现用于执行积分A / D转换和用于执行循环A / D转换的第二A / D转换操作的第一A / D转换操作 。 此外，在第一A / D转换操作中，由于在输出信号的积分中使用的电容器的容量大于用于存储输入模拟信号和标准参考电压的电容器的容量，所以模拟信号 在积分A / D转换中输入根据容量比衰减并进行采样和积分。 因此，根据电容器的容量比，在积分A / D转换中输出的模拟信号的电压范围也降低，因此可以以单端配置构建A / D转换器。

公开(公告)号：US09209828B2

公开(公告)日：2015-12-08

申请号：US14419642

申请日：2013-08-16

申请人： MISSING LINK ELECTRONICS, INC.

发明人： Nils Endric Schubert ,  Johannes Brock ,  Christian Grumbein

IPC分类号： H03M3/00 ,  G06F17/50 ,  H03M7/30

CPC分类号： H03M3/458 ,  G06F17/5022 ,  G06F17/5054 ,  G06F17/5063 ,  H03M3/30 ,  H03M3/392 ,  H03M3/46 ,  H03M7/3015

摘要： An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

摘要翻译： 电子系统包括可配置的处理装置。 可配置处理装置包括执行数字处理的处理器，接收数字信号的第一输入端，发送数字信号的第一输出端和在模拟信号和数字信号之间转换的转换器。 该转换器包括一个Δ-Σ调制器。

公开(公告)号：US20150215553A1

公开(公告)日：2015-07-30

申请号：US14420258

申请日：2013-08-07

申请人： Innovaciones Microelectrónicas S.L.

发明人： Fernando Medeiro Hidalgo ,  Rafael Domínguez Castro

IPC分类号： H04N5/378 ,  H04N5/374 ,  H03M1/14 ,  H03M1/00 ,  H03M1/06

CPC分类号： H04N5/378 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/145 ,  H03M1/365 ,  H03M1/56 ,  H03M3/39 ,  H03M3/46 ,  H04N5/374

摘要： The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.

摘要翻译： 本发明涉及一种二级或多级模数转换器。 转换器优选地包括在第一级中的增量ADC。 增量ADC包括积分器和比较器。 在由比较器执行预定数量的比较之后，将适当缩放的积分器的输出提供给进一步采样的第二级。 具体而言，缩放增益与积分器增益成反比。 第二个ADC执行剩余的最低有效位的转换，然后组合两个级的输出。 此外，为多级ADC提供校准和校正方法。

公开(公告)号：US09071259B2

公开(公告)日：2015-06-30

申请号：US14471418

申请日：2014-08-28

申请人： DENSO CORPORATION

发明人： Tomohiro Nezuka

IPC分类号： H03M3/00 ,  H03M1/00

CPC分类号： H03M1/001 ,  H03M3/384 ,  H03M3/422 ,  H03M3/43 ,  H03M3/438 ,  H03M3/454 ,  H03M3/46 ,  H03M3/496

摘要： An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter.

摘要翻译： 在通过多个环路滤波器之后，由量化器对输入信号进行量化。 最后一级环路滤波器由用于产生输出信号的运算放大器，用于对输入信号进行采样的采样电容器，用于对由电容器采样的信号进行积分的积分电容器和用于切换信号路径的多个开关构成。 控制电路控制开关的通/断状态以对采样电容器和积分电容器进行放电，并使环路滤波器重复采样操作和积分操作多次。 控制电路最后将采样电容器和积分电容器连接到与积分操作时间的状态相反的状态，并接通转换开关，使得A / D转换器对输出信号的输出信号进行A / D转换 环路滤波器。

公开(公告)号：US20150116137A1

公开(公告)日：2015-04-30

申请号：US14394297

申请日：2013-04-11

申请人： PR Electronics A/S

发明人： Stig Lindemann ,  Mads Kolding Nielsen

IPC分类号： H03M1/46

CPC分类号： H03M1/46 ,  G01D3/022 ,  H03M1/0827 ,  H03M1/1042 ,  H03M3/388 ,  H03M3/46 ,  H03M7/302

摘要： A system for galvanic isolation between an analog input signal and an analog output signal, which system performs an analog to digital conversion of the input signals into input digital data. As a result, input parameters can be corrected in a nearly perfect way.

摘要翻译： 一种用于在模拟输入信号和模拟输出信号之间进行电隔离的系统，该系统将输入信号的模数转换转换为输入数字数据。 因此，输入参数可以以几乎完美的方式进行修正。