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公开(公告)号：US20190190534A1
公开(公告)日：2019-06-20
申请号：US16055193
申请日：2018-08-06
发明人： YONG-WOO KIM , DAI SHI , EUN SEOK SHIN
CPC分类号： H03M3/428 , H03M3/502 , H03M7/3026
摘要： A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.
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公开(公告)号：US20190165820A1
公开(公告)日：2019-05-30
申请号：US15828106
申请日：2017-11-30
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
摘要： A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
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3.发明申请公开(公告)号：US20180205352A1
公开(公告)日：2018-07-19
申请号：US15873532
申请日：2018-01-17
申请人： KAPIK INC.
IPC分类号： H03F3/217 , H03F1/06 , H03F3/24 , H03L7/081 , H03M3/02 , H03M7/30 , H04B14/06 , H04L27/36 , G06F7/60
CPC分类号： H03F3/2171 , G06F7/602 , H03F1/06 , H03F3/185 , H03F3/2173 , H03F3/24 , H03F2200/03 , H03F2200/331 , H03L7/0816 , H03M3/02 , H03M3/502 , H03M7/3011 , H03M7/3015 , H04B14/062 , H04L27/36
摘要： An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.
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公开(公告)号：US09853654B2
公开(公告)日：2017-12-26
申请号：US14631578
申请日：2015-02-25
CPC分类号： H03M1/0626 , H03M1/002 , H03M1/687 , H03M3/368 , H03M3/502 , H03M7/3042
摘要： In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.
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公开(公告)号：US20170170838A1
公开(公告)日：2017-06-15
申请号：US15366069
申请日：2016-12-01
CPC分类号： H03L7/191 , H03F1/08 , H03F1/30 , H03F1/3247 , H03F1/3258 , H03F3/2175 , H03F3/45475 , H03F2200/447 , H03F2203/45528 , H03K19/21 , H03M1/1038 , H03M1/785 , H03M3/358 , H03M3/40 , H03M3/402 , H03M3/502 , H03M7/3026 , H03M7/3033 , H04L7/0029 , H04L7/005 , H04L27/362
摘要： An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element.
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6.发明申请MISMATCH AND INTER SYMBOL INTERFERENCE (ISI) SHAPING USING DYNAMIC ELEMENT MATCHING 有权使用动态元素匹配的错配和内部符号干扰（ISI）形状公开(公告)号：US20170033802A1
公开(公告)日：2017-02-02
申请号：US15221028
申请日：2016-07-27
发明人： Vincent O'Brien , Brendan Mullane , Tony Scanlan
IPC分类号： H03M3/00
摘要： The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of ‘on’ and ‘off’ transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.
摘要翻译： 本发明在数据转换器中的不匹配和ISI整形。 本发明提供一种并入失配和符号间干扰整形的动态元件匹配技术。 提供数字解码器，其控制“开”和“关”转换的数量，使得所得信号不包含噪声或失真。 本发明的元件选择技术适用于高分辨率多位连续时间过采样数据转换器。
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公开(公告)号：US09362943B2
公开(公告)日：2016-06-07
申请号：US14695385
申请日：2015-04-24
发明人： Akira Yasuda , Jun-ichi Okamura
摘要： Provided is a data converter which is provided with a clock signal input part which inputs a clock signal, and an input part which inputs an input signal, a sampling part which, in response to the clock signal input to the clock signal input part, performs sampling of the input signal input to the input part, and a signal processing part which performs signal processing according to the sampling cycle and outputs an output signal, wherein when the cycle of the clock signal input to the clock signal input part becomes longer, the output signals output by the signal processing part are reduced.
摘要翻译： 提供了一种数据转换器，其设置有输入时钟信号的时钟信号输入部分和输入输入信号的输入部分，响应于输入到时钟信号输入部分的时钟信号执行的采样部分 输入到输入部的输入信号的采样，以及根据采样周期执行信号处理的信号处理部，输出输出信号，其中，当输入到时钟信号输入部的时钟信号的周期变长时， 减少由信号处理部输出的输出信号。
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公开(公告)号：US09172393B2
公开(公告)日：2015-10-27
申请号：US14633888
申请日：2015-02-27
申请人： Broadcom Corporation
发明人： David Stoops , Min Gyu Kim , Vinod Jayakumar
IPC分类号： H03M3/00
摘要： Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.
摘要翻译： 公开了用于将数字输入信号转换为模拟输出信号的方法，系统和装置。 第一Δ-Σ调制器接收共模参考信号并产生共模控制信号。 数据Δ-Σ调制器接收数字输入信号并产生调制数字输入信号。 洗牌器接收调制数字输入信号和共模控制信号，并产生混洗数字输入信号。 数模转换器（DAC）具有多个三电平单元DAC元件，每个三电平单元DAC元件接收混频数字输入信号的相应部分作为第一输入信号，并接收第二和第三输入信号。 三电平单元DAC元件具有耦合在一起的第一输出产生第一输出信号和耦合在一起的第二输出产生第二输出信号。 运算放大器接收第一和第二输出信号并产生模拟输出信号。
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9.发明申请DELTASIGMA D/A CONVERTER, SIGNAL PROCESSING CIRCUIT INCLUDING THE SAME, AND ELECTRONIC APPARATUS 有权DELTASIGMA D / A转换器，包括其的信号处理电路和电子设备公开(公告)号：US20150280735A1
公开(公告)日：2015-10-01
申请号：US14674523
申请日：2015-03-31
申请人： ROHM CO., LTD.
发明人： Kinji ITO
CPC分类号： H03M3/502 , H03M1/0631 , H03M3/368 , H03M7/3037 , H04R3/00 , H04R2499/13
摘要： A ΔΣ D/A converter for converting a digital input data to an analog output signal, includes: a ΔΣ modulator configured to generate a first data by ΔΣ-modulating the digital input data; a digital filter configured to generate a second data by smoothing the first data; and a D/A converter configured to convert the second data to the analog output signal.
摘要翻译： A＆Dgr＆＆ D / A转换器，用于将数字输入数据转换为模拟输出信号，包括：＆Dgr;＆Sgr; 调制器，被配置为通过＆Dgr＆amp; Sgr-调制数字输入数据生成第一数据; 数字滤波器，被配置为通过平滑所述第一数据来生成第二数据; 以及配置成将第二数据转换成模拟输出信号的D / A转换器。
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公开(公告)号：US08823569B2
公开(公告)日：2014-09-02
申请号：US14106512
申请日：2013-12-13
申请人： Julian Jenkins , Torsten Lehmann
发明人： Julian Jenkins , Torsten Lehmann
CPC分类号： H03M3/502 , H03M1/00 , H03M1/0641 , H03M1/0665 , H03M1/0673 , H03M1/747 , H03M1/785
摘要： An apparatus and method for digital-to-analog conversion. A digital-to-analog converter includes a sampler for resampling a digital signal and a DAC array. The DAC array includes a sequencer, a unit element activator, and an array of one-bit DACs (unit elements). The unit elements are activated in a cyclical sequence, based on the resampled digital signal. Unit elements in the sequence may be skipped, based on a disruption probability. The disruption probability may be determined randomly, or pseudo-randomly. Output signals of the unit elements are summed or averaged to form an analog signal. The converter may include a filter to filter the analog signal.
摘要翻译： 一种用于数模转换的装置和方法。 数模转换器包括用于重新采样数字信号的采样器和DAC阵列。 DAC阵列包括定序器，单元元件激活器和一位DAC（单元元件）阵列。 基于重新采样的数字信号，单位元件以循环序列被激活。 可以基于中断概率来跳过序列中的单元元素。 可以随机地或随机地确定中断概率。 将单位元件的输出信号求和或平均以形成模拟信号。 转换器可以包括滤波器以对模拟信号进行滤波。
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