公开(公告)号：US09667288B1

公开(公告)日：2017-05-30

申请号：US14965535

申请日：2015-12-10

申请人： Marvell International Ltd.

发明人： Swaroop Venkatesh ,  Vijay Ahirwar

IPC分类号： H04B1/10 ,  H04B1/00 ,  H03H15/00 ,  H04B1/04 ,  H03H11/04 ,  H04B15/06 ,  H04B15/02

CPC分类号： H04B1/1036 ,  H03H11/04 ,  H03H17/025 ,  H03H17/0294 ,  H03H17/04 ,  H03H2011/0488 ,  H03H2015/007 ,  H04B1/001 ,  H04B1/0475 ,  H04B1/1027 ,  H04B1/109 ,  H04B1/525 ,  H04B15/02 ,  H04B15/06 ,  H04B2001/1063 ,  H04B2215/064

摘要： The present disclosure includes systems and techniques relating to time-varying notch filter. In one implementation, an apparatus includes a time-variant notch filter and a controller. The time-variant notch filter includes a notch depth and a notch bandwidth centered on a notch frequency. At least one of the notch depth or the notch bandwidth is based on a coefficient of the notch filter. The controller is configured to estimate a power of a packet being received and compare the estimated power of the packet to a predetermined threshold. The controller is also configured to set, conditioned on determining that the estimated power of the packet is greater than the predetermined threshold, a value of the coefficient to a first value such that the packet bypasses the time-variant notch filter.

公开(公告)号：US09407379B2

公开(公告)日：2016-08-02

申请号：US14516546

申请日：2014-10-16

申请人： QUALCOMM Incorporated

发明人： Wing Fat Andy Lau ,  Jorge Andres Garcia ,  David Zixiang Yang ,  Ahmed Abdel Monem Youssef

IPC分类号： H04B1/16 ,  H04B15/06 ,  H03D7/14

CPC分类号： H04B15/06 ,  H03D7/1458 ,  H03D7/1483 ,  H03F2200/165 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541 ,  H04B2215/064

摘要： An apparatus for reducing a harmonic response in an electronic circuit is provided. The apparatus includes an RF input configured to provide a first signal operating at a radio frequency. The apparatus includes a local oscillator configured to produce a second signal operating at a local oscillator (LO) frequency. The apparatus includes a switching mixer configured to mix the first and second signals. The apparatus includes a notch filter comprising an inductor and a capacitor connected in parallel. The notch filter is directly coupled to an input of the switching mixer in series. The notch filter is tuned such that its resonant frequency is a harmonic of the LO frequency signal. In an aspect, the apparatus also includes a transformer configured to provide the first signal. In an aspect the apparatus also includes a second notch filter comprising a second inductor and a second capacitor connected in parallel.

摘要翻译： 提供一种用于减少电子电路中的谐波响应的装置。 该装置包括被配置为提供以射频工作的第一信号的RF输入。 该装置包括配置成产生以本地振荡器（LO）频率工作的第二信号的本地振荡器。 该装置包括配置成混合第一和第二信号的切换混合器。 该装置包括陷波滤波器，该陷波滤波器包括并联连接的电感器和电容器。 陷波滤波器与串联的开关混频器的输入端直接耦合。 调谐陷波滤波器使其谐振频率为LO频率信号的谐波。 在一方面，该装置还包括被配置为提供第一信号的变压器。 在一方面，该装置还包括第二陷波滤波器，其包括并联连接的第二电感器和第二电容器。

公开(公告)号：US09184856B2

公开(公告)日：2015-11-10

申请号：US11043235

申请日：2005-01-26

申请人： Hideyuki Usui ,  Hideyuki Tagai ,  Osamu Yamamoto ,  Kohji Inoue ,  Kazuo Fujii ,  Kohhei Shibata

发明人： Hideyuki Usui ,  Hideyuki Tagai ,  Osamu Yamamoto ,  Kohji Inoue ,  Kazuo Fujii ,  Kohhei Shibata

IPC分类号： H04B1/00 ,  H04B15/00 ,  H04B15/02 ,  H04W16/14

CPC分类号： H04B15/02 ,  H04B2215/064 ,  H04W16/14

摘要： Wireless noise is detected within a time period specifically held after a data packet is wirelessly communicated, where no data is purposefully wirelessly communicated during this time period. The time period may be an inter-frame space (IFS) period within which no data is to be wirelessly communicated, and that is a period waited for prior to accessing a wireless medium over which data is wirelessly communicated. One or more actions are performed to counteract the noise. The frequency at which a liquid crystal display is being driven may be decreased so that harmonics caused thereby that caused the noise are no longer within the wireless communication frequency range. An opposite-in-phase version of the noise may also or alternatively be combined with a signal when data is subsequently wirelessly received. The signal includes a data component and a noise component, the opposite-in-phase version of the noise canceling out the noise component.

摘要翻译： 在无线通信数据分组之后的特定时间段内检测无线噪声，在该时间段内没有有目的地无线地传送数据。 该时间段可以是不在其中无数据被无线传送的帧间空间（IFS）周期，并且这是在接入无线介质之前等待的时间段，数据被无线传送。 执行一个或多个动作来抵消噪声。 液晶显示器被驱动的频率可能会降低，从而导致噪声引起的谐波不再在无线通信频率范围内。 当数据随后被无线地接收时，噪声的相反相位版本也可以或者可选地与信号组合。 该信号包括数据分量和噪声分量，噪声的相反相位版本消除了噪声分量。

公开(公告)号：US20150139376A1

公开(公告)日：2015-05-21

申请号：US14130048

申请日：2012-07-02

申请人： Jan Johannes Maria Van Den Elzen

发明人： Jan Johannes Maria Van Den Elzen

IPC分类号： H04B15/02 ,  H04L7/00

CPC分类号： H04B15/02 ,  H04B2215/064 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/033 ,  H04L2007/047

摘要： A signal propagation system for communicating timing information comprises a processing resource (300) arranged to generate a first timing signal for communicating the timing information, the first timing signal having a first frequency spectrum associated therewith. An electronic circuit (110) is provided having an input for receiving the timing information. An electrical connection (310) between the processing resource (300) and the electronic circuit (110) is also provided. A signal transformation module (304) for communicating the timing information, and the signal transformation module (304) is arranged to translate the first timing signal into a second timing signal for communicating the timing information. The second timing signal has a second frequency spectrum associated therewith that comprises fewer harmonics than the first timing signal, thereby reducing electromagnetic energy emitted by the electrical connection.

摘要翻译： 用于传送定时信息的信号传播系统包括被配置为产生用于传送定时信息的第一定时信号的处理资源（300），第一定时信号具有与之相关联的第一频谱。 提供具有用于接收定时信息的输入的电子电路（110）。 还提供了处理资源（300）和电子电路（110）之间的电连接（310）。 用于传送定时信息的信号变换模块（304）和信号变换模块（304）被布置成将第一定时信号转换成用于传送定时信息的第二定时信号。 第二定时信号具有与其相关联的第二频谱，其包括比第一定时信号更少的谐波，从而减少由电连接发射的电磁能。

公开(公告)号：US08724649B2

公开(公告)日：2014-05-13

申请号：US12325401

申请日：2008-12-01

申请人： Nir Tal ,  Yaniv Tzoreff ,  Moran Amidan ,  Gregory Lerner ,  Ronen Isaac ,  Roi Faust

发明人： Nir Tal ,  Yaniv Tzoreff ,  Moran Amidan ,  Gregory Lerner ,  Ronen Isaac ,  Roi Faust

IPC分类号： H04L12/413 ,  H04B3/32

CPC分类号： H04L12/413 ,  H04B3/32 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A novel and useful apparatus for and method of distributed coexistence for mitigating interference in a single chip radio and/or a multi-radio (i.e. multi-transceiver) communications device. The invention enables coexistence ‘friendly’ radio IPs having frequency agility in that they are capable of shifting their clock frequencies thereby avoiding frequency bands of potential victim radios. Frequency agility on the aggressor radio side (rather than by mitigating the effect of interference on the victim radio side) prevents harmonics from the aggressor's clock scheme from falling in the operating frequency band of the victim radio, and in turn causing degradation to its performance. Each aggressor radio, based on information received from other radios, configures the root clock frequency of its RX and/or TX chain clock generation circuits.

摘要翻译： 一种用于减轻单芯片无线电和/或多无线电（即多收发机）通信设备中的干扰的分布式共存的新颖有用的装置和方法。 本发明使具有频率敏捷性的共存“友好”无线IP成为能够移动其时钟频率从而避免潜在的受害者无线电的频带的共存的无线IP。 侵略者无线电侧的频率敏捷性（而不是通过减轻干扰对受害者无线电侧的影响）可以防止侵略者时钟方案的谐波落入受害者无线电的工作频带，从而导致其性能下降。 每个侵略者无线电设备基于从其他无线电接收的信息，配置其RX和/或TX链时钟生成电路的根时钟频率。

公开(公告)号：US08463223B2

公开(公告)日：2013-06-11

申请号：US13524909

申请日：2012-06-15

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/00

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收信道选择信号的输入端，其中微控制器提供时钟控制信号以响应于信道选择输入来动态地控制时钟信号的频率，以减少由时钟信号产生的次谐波的干扰 模拟接收机。

公开(公告)号：US08422964B2

公开(公告)日：2013-04-16

申请号：US13104822

申请日：2011-05-10

申请人： Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu Shankar Srinivasan

发明人： Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu Shankar Srinivasan

IPC分类号： H04B1/40

CPC分类号： H04B1/109 ,  H04B1/0003 ,  H04B1/28 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064 ,  H04L27/2649

摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

公开(公告)号：US20120274367A1

公开(公告)日：2012-11-01

申请号：US13391893

申请日：2010-08-24

申请人： Kiat Seng Yeo ,  Jian Guo Ma

发明人： Kiat Seng Yeo ,  Jian Guo Ma

IPC分类号： H03B19/00

CPC分类号： H04B1/28 ,  H03D7/163 ,  H03D7/166 ,  H04B15/04 ,  H04B2215/064

摘要： In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal. The front-end transceiver may further include an oscillator signal generator respectively coupled to the first receiver frequency converter and to the receiver direct conversion stage so as to provide a first oscillator signal with a first oscillator frequency to the first receiver frequency converter and a first stabilizing signal with a first stabilizing frequency to the receiver direct conversion stage; wherein the oscillator signal generator may be configured so that the first oscillator frequency of the first oscillator signal may be selected such that any integer multiple of the first oscillator frequency of the first oscillator signal may be different from any integer multiple of the receiver frequency of the received signal. The front-end transceiver may also include a transmitter path.

摘要翻译： 在一个实施例中，可以提供前端收发器。 前端收发器可以包括接收器路径，包括被配置为将具有接收机频率的接收信号转换为具有第一接收机中频的第一接收机中间信号的第一接收机频率转换器; 以及接收器直接转换级，其耦合到所述第一接收机频率转换器，以便接收所述第一接收机中间信号。 前端收发器还可以包括分别耦合到第一接收机频率转换器和接收机直接转换级的振荡器信号发生器，以便向第一接收机频率转换器提供具有第一振荡器频率的第一振荡器信号和第一稳定 信号具有第一稳定频率到接收机直接转换级; 其中振荡器信号发生器可以被配置为使得可以选择第一振荡器信号的第一振荡器频率，使得第一振荡器信号的第一振荡器频率的任何整数倍可以不同于第一振荡器信号的接收机频率的任何整数倍 接收信号。 前端收发器还可以包括发射机路径。

公开(公告)号：US08013628B2

公开(公告)日：2011-09-06

申请号：US12381431

申请日：2009-03-12

申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。

公开(公告)号：US20110115537A1

公开(公告)日：2011-05-19

申请号：US12621050

申请日：2009-11-18

申请人： Michael Robert May ,  Russell Croman ,  Younes Djadi ,  Scott Thomas Haban

发明人： Michael Robert May ,  Russell Croman ,  Younes Djadi ,  Scott Thomas Haban

IPC分类号： H03K5/12

CPC分类号： H04B15/04 ,  H04B2215/064 ,  H04B2215/065 ,  H04L7/0045 ,  H04L7/0091

摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.

摘要翻译： 实施例包括用于对输入信号进行重新计时的电路装置和方法。 在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。 数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。