公开(公告)号：USRE34896E

公开(公告)日：1995-04-04

申请号：US52189

申请日：1991-05-29

申请人： Jean L. J. Calvignac ,  Jacques M. C. Feraud ,  Jean-Marie L. Munier

发明人： Jean L. J. Calvignac ,  Jacques M. C. Feraud ,  Jean-Marie L. Munier

IPC分类号： G06F13/40 ,  H04L12/52 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L12/525 ,  G06F13/4022

摘要： A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slots are assigned to each user line, the structure of the two slots is identical for all types of user lines and includes an n-bit data slot having a variable number x of valid bits depending upon the line speed of the user line assigned to the data slot and indicated by a variable delimiter pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n--x--1) bits set at the second binary value (0) adjacent to said first delimiting bit, and an n-bit control slot having a first bit used as a global validation bit in case the data slot comprises n valid bits (x.dbd.n), this bit being set at the first binary value (1) when the data slot comprises n valid bits and at the second binary value (0) if it comprises less than n valid bits, and the n--following bits are used for exchanging control information.

摘要翻译： 一种多路复用接口，用于经由发送和接收同步多路复用链路将通信控制器的线路扫描装置（1）与用户线互连。 在同步帧中交换数据和控制位，其中至少两个时隙被分配给每个用户线，两个时隙的结构对于所有类型的用户线是相同的，并且包括具有可变数目x的n位数据时隙 有效位取决于分配给数据时隙的用户行的线速度，并且由可变分隔符模式指示，该可变分隔符模式包括在与数据位相邻的第一二进制值（1）和（nx-1）位设置下设置的第一定界位 在与所述第一定界位相邻的第二二进制值（0）处，以及在数据时隙包括n个有效位（x = n）的情况下具有用作全局验证位的第一位的n位控制时隙，该位为 如果数据时隙包括n个有效位，并且如果其包括小于n个有效位，则设置在第二二进制值（1）处，并且在第二个二进制值（0）处，并且将n个后续位用于交换控制信息。

公开(公告)号：US5107260A

公开(公告)日：1992-04-21

申请号：US482964

申请日：1990-02-22

申请人： Holger Meissner, deceased ,  Werner Stoerzbach

发明人： Holger Meissner, deceased ,  Werner Stoerzbach

IPC分类号： H04L12/52

CPC分类号： H04L12/525

摘要： Method and arrangement for transmitting data between a central data station and a plurality of data terminal equipment in a local area network. In order to achieve fast data transmission for simultaneous data lines in a local area network between a central data station and a plurality of data terminals upon interposition of a network node, whereby the known HDLC (high level data link control) data transmission procedure is combined with a data transmission method for data transmission wherein every status change of the binary coded data has a transmission pulse alternating in operational sign allocated to it, a concentrator is utilized as the network node. This concentrator regenerates the incoming HDLC data packet and then transparently forwards them to their desination.

摘要翻译： 在局域网中的中央数据站与多个数据终端设备之间传输数据的方法和装置。 为了在插入网络节点时在中央数据站和多个数据终端之间的局域网中实现快速数据传输，由此组合已知的HDLC（高级数据链路控制）数据传输过程 利用用于数据传输的数据传输方法，其中二进制编码数据的每个状态改变具有交替分配给其的操作符号的传输脉冲，集中器被用作网络节点。 该集中器重新生成传入的HDLC数据包，然后透明地将其转发到它们的定位。

公开(公告)号：US4958342A

公开(公告)日：1990-09-18

申请号：US435276

申请日：1989-11-09

申请人： Stephen J. Williams ,  Elden D. Traster

发明人： Stephen J. Williams ,  Elden D. Traster

IPC分类号： H04L12/52

CPC分类号： H04L12/525

摘要： A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of the fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

摘要翻译： 复用数据通信系统（10）提供多个微型计算机终端（12）与主计算机（30）之间的通信。 来自微型计算机（12）的通信在两个DMI接口（22和24）之间的T1线路（26）上被复用。 DMI接口（24）包括自适应数字网络接口（62），其以串行方式处理复用数据，从而允许对数据进行成帧和处理协议信息的灵活性。 自适应数字网络接口（62）中的程序控制部分地由三个计数器（266,268和272）的状态执行，并且存在于fifo存储器（112）的输出端的位允许增加的处理速度。 此外，通过使用允许自适应数字网络接口（62）的元件的同时选通和使能的指令集来提高处理速度。

公开(公告)号：US4691297A

公开(公告)日：1987-09-01

申请号：US740977

申请日：1985-06-04

申请人： Pieter Wolff

发明人： Pieter Wolff

IPC分类号： G06F13/38 ,  H03M9/00 ,  H04L12/52 ,  G11C7/00 ,  G11C19/00

CPC分类号： H04L12/525 ,  G06F13/38 ,  H03M9/00

摘要： For receiving and/or transmitting serially appearing binary signals to and from a processing device containing a microcomputer or microprocessor, the signal receiving lines carrying the serially appearing binary signals are connected by way of individual flip-flop elements to an input of the microcomputer or microprocessor, and signal output lines are connected by way of individual flip-flop elements to respective outputs of the microcomputer or microprocessor. In the microcomputer or microprocessor, the serial appearing binary signals are converted into parallel signals for processing, and the processed parallel signals are reconverted into serial signals for signal transmission.

摘要翻译： 为了向包含微计算机或微处理器的处理装置接收和/或发送串行显示的二进制信号，承载串行出现的二进制信号的信号接收线路通过各个触发器元件连接到微计算机或微处理器的输入端 并且信号输出线通过单独的触发器元件连接到微计算机或微处理器的相应输出。 在微计算机或微处理器中，串行出现的二进制信号被转换成并行信号进行处理，并且处理后的并行信号被重新转换为串行信号用于信号传输。

公开(公告)号：US4661966A

公开(公告)日：1987-04-28

申请号：US777021

申请日：1985-09-17

申请人： Stanley M. Schreiner

发明人： Stanley M. Schreiner

IPC分类号： H04J3/07 ,  H04J3/16 ,  H04L12/52 ,  H04L7/04

CPC分类号： H04J3/07 ,  H04J3/1647 ,  H04L12/525

摘要： Two data equipments are connected by switching equipment which supplies high speed lines for a modified data signal and a stuff control signal. A system clock or system clock derived signal is used in a stuffing pattern generator which generates a stuff control signal for one of the high speed lines. The stuffing pattern generator also controls the read terminal of a first buffer register receiving input data from a first equipment written into the register under the control of a clock generated from the system clock. The output from the first buffer register includes stuffing bits as well as data and the data and stuff signal is fed through a high speed line to a second buffer register. The write terminal of the second buffer register receives the stuff control signal to control input to the register and causes deletion of the stuff bits. The read terminal of the second buffer register is under control of the clock derived from the system clock to control the register output to the second equipment.

摘要翻译： 两个数据设备通过为修改的数据信号和填充控制信号提供高速线路的开关设备连接。 系统时钟或系统时钟导出信号用于填充图案发生器，其产生用于高速线之一的填充控制信号。 填充图案发生器还控制第一缓冲寄存器的读取端子，其在从系统时钟产生的时钟的控制下，从写入寄存器的第一设备接收输入数据。 来自第一缓冲寄存器的输出包括填充位以及数据，并且数据和填充信号通过高速线馈送到第二缓冲寄存器。 第二缓冲寄存器的写入端子接收填充控制信号以控制对寄存器的输入，并导致填充位的删除。 第二缓冲寄存器的读终端受到从系统时钟导出的时钟的控制，以控制寄存器输出到第二设备。

公开(公告)号：US4389642A

公开(公告)日：1983-06-21

申请号：US279323

申请日：1981-07-01

申请人： William M. Kahn

发明人： William M. Kahn

IPC分类号： H04L12/52 ,  H04Q11/04 ,  H04Q9/00

CPC分类号： H04L12/525 ,  H04Q11/04

摘要： Eight input ports are sampled once every eight clock pulse intervals, and the samples are multiplexed to an eight-bit collecting register that stores data bit signals from selected input ports in cells corresponding to the location of designated output ports selected in accordance with selection signals stored in a 64-bit RAM having eight-bit words that may be changed to designate the connections among input ports and output ports for data transfer. The data signals in the eight-bit collecting register are transferred to an output holding register in cells corresponding to respective output ports that are released in response to the sample signal.

摘要翻译： 八个输入端口每八个时钟脉冲间隔被采样一次，并且样本被复用到一个八位收集寄存器，该八位收集寄存器存储来自所选输入端口的数据位信号，该单元对应于根据存储的选择信号选择的指定输出端口的位置 在具有八位字的64位RAM中，可以改变它们以指定用于数据传输的输入端口和输出端口之间的连接。 8位收集寄存器中的数据信号被传送到与响应于采样信号而释放的相应输出端口对应的单元中的输出保持寄存器。

公开(公告)号：US3989892A

公开(公告)日：1976-11-02

申请号：US592958

申请日：1975-07-03

申请人： Shinichiro Yoshida ,  Yoshitsugu Watanabe ,  Yuji Hayano ,  Susumu Ohara ,  Takuhito Kojima

发明人： Shinichiro Yoshida ,  Yoshitsugu Watanabe ,  Yuji Hayano ,  Susumu Ohara ,  Takuhito Kojima

IPC分类号： H04Q11/04 ,  H04L5/24 ,  H04L12/52 ,  H04L5/22

CPC分类号： H04L5/24 ,  H04L12/525

摘要： A line concentrator for a time division data switching exchange. Asynchronous and synchronous data signals generated at asynchronous and synchronous data terminals are subjected to known multi-point and synchronous sampling to become a train of bit-multiplexed first asynchronous and synchronous data channel signals. Responsive to a train of bit-interleaved read-in pulse groups timed relative to the respective synchronous data signals, an arithmetic unit stores the data channel signals in an octet memory according to the asynchronous and synchronous data terminals. Responsive to a train of read-out pulses appearing for the respective data terminals, the arithmetic unit reproduces groups of uninterleaved data channel signals for each data terminal and composes the reproduced data channel signals into a train of second asynchronous and synchronous data channel signals given by a common and uninterleaved bit format. The line concentrator is readily modified for decomposition of a train of asynchronous and synchronous data channel signal groups of the bit format into replicas of the original data signals.

摘要翻译： 用于时分数据交换的线路集线器。 在异步和同步数据终端产生的异步和同步数据信号经受已知的多点和同步采样，成为一列位复用的第一异步和同步数据信道信号。 响应于相对于各个同步数据信号定时的一串比特交错读入脉冲组，算术单元根据异步和同步数据终端将数据信道信号存储在八位字节存储器中。 响应于对于各个数据终端出现的读出脉冲序列，运算单元再现每个数据终端的未交织的数据信道信号组，并将再现的数据信道信号组成由一系列第二异步和同步数据信道信号，由 一个常见的和未交织的位格式。 线集中器易于修改，用于将比特格式的异步和同步数据信道信号组的序列分解为原始数据信号的复本。

公开(公告)号：US4935925A

公开(公告)日：1990-06-19

申请号：US234262

申请日：1988-08-19

申请人： Stephen J. Williams ,  Elden D. Traster

发明人： Stephen J. Williams ,  Elden D. Traster

IPC分类号： H04L12/52

CPC分类号： H04L12/525

摘要： A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of a fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

摘要翻译： 复用数据通信系统（10）提供多个微型计算机终端（12）与主计算机（30）之间的通信。 来自微型计算机（12）的通信在两个DMI接口（22和24）之间的T1线路（26）上被复用。 DMI接口（24）包括自适应数字网络接口（62），其以串行方式处理复用数据，从而允许对数据进行成帧和处理协议信息的灵活性。 自适应数字网络接口（62）中的程序控制部分地由三个计数器（266,268和272）的状态和存在于fifo存储器（112）的输出端的位执行，从而允许增加的处理速度。 此外，通过使用允许自适应数字网络接口（62）的元件的同时选通和使能的指令集来提高处理速度。

公开(公告)号：US4849962A

公开(公告)日：1989-07-18

申请号：US153610

申请日：1988-02-08

申请人： Shigeki Morimoto ,  Toshiaki Koyama

发明人： Shigeki Morimoto ,  Toshiaki Koyama

IPC分类号： H04L29/04 ,  H04L5/00 ,  H04L12/52 ,  H04L29/10

CPC分类号： H04L12/525 ,  H04L5/00

摘要： In communications control unit for sequentially scanning a plurality of line sets to which full-duplex lines are connected, for reading out line control word provided in correspondence to the line from a memory when a data transmission/reception request exists in the line set, and for executing the data transmitting and receiving operations with the relevant line set, one line control word including both of transmission control information and reception control information is read out in the time slot assigned to one full-duplex line, and the data transmitting and receiving operations are simultaneously executed.

摘要翻译： 在通信控制单元中，用于顺序地扫描连接有全双工线路的多个线路组，用于当线路组中存在数据发送/接收请求时从存储器读出对应于线路提供的线路控制字，以及 为了执行与相关行集合的数据发送和接收操作，在分配给一个全双工线路的时隙中读出包括传输控制信息和接收控制信息两者的一行控制字，并且数据发送和接收操作 同时执行。

公开(公告)号：US4799256A

公开(公告)日：1989-01-17

申请号：US826691

申请日：1986-02-06

申请人： Renate Mattis ,  Gunther Seidel ,  Heinrich belhack ,  Russel D. Homer

发明人： Renate Mattis ,  Gunther Seidel ,  Heinrich belhack ,  Russel D. Homer

IPC分类号： H04L12/52 ,  H04M7/06 ,  H04Q11/04 ,  H04Q3/545

CPC分类号： H04Q11/0407 ,  H04L12/525

摘要： A circuit arrangement for telecommunication installations, in particular, telephone exchange installations is disclosed in which type information is sent ahead of each communication to be transmitted. In bidirectional communication transmission with different possible communication types, type information announcing the respective communication type is sent ahead. In the receiving equipment the beginning of the arrival of type information is recognized and immediately, that is, almost simultaneously, an assortment of type-specific message corresponding to each of the possible communication types is transmitted in the opposite direction, of which each indicates the readiness or non-readiness for receiving a communication of the respective type. From this and from the transmitted type information it is recognized following the transmission of type information and messages on both sides independently of each other but concordantly whether a communication transmission will subsequently occur, cannot occur or will be postponed to a later time.

摘要翻译： 公开了一种用于电信设备的电路装置，特别是电话交换设备，其中在要发送的每个通信之前发送类型信息。 在具有不同可能通信类型的双向通信传输中，向前发送通知相应通信类型的类型信息。 在接收设备中，类型信息到达的开始被立即识别，也就是几乎同时地，与各种可能的通信类型相对应的类型特定消息的分类以相反的方向发送，其中每个指示 准备或不准备接收相应类型的通信。 从这个和从发送的类型信息中，在彼此独立地发送类型信息和消息之后，一致地识别通信传输是否将随后发生，不能发生或将被推迟到稍后的时间被识别。