公开(公告)号：US20190131999A1

公开(公告)日：2019-05-02

申请号：US16092883

申请日：2017-04-12

申请人： Forschungsverbund Berlin e.V.

发明人： Florian HÜHN

IPC分类号： H03M3/00 ,  H04L27/20 ,  H03F3/217 ,  H03F3/387

CPC分类号： H03M3/404 ,  H03F3/189 ,  H03F3/217 ,  H03F3/38 ,  H03F3/387 ,  H03F2200/339 ,  H04L27/2092

摘要： The present invention relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier.The modulator (100) comprises a pulse shaper (110) and a control unit (120) for controlling the pulse shaper (110) to convert an input signal into a bit stream (130) configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper (110) can represent a respective amplitude value of the input signal with different bit patterns. The bit pattern respectively used by the pulse shaper is determined by the control unit (120) by means of a corresponding, associated control command. The modulator (100) is characterized in that in the control unit (120) an assignment (160) of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier (400) is stored or at least is provided in that the control unit (120) selects a control command per clock by means of the assignment (160) and the amplitude value of the input signal and drives the pulse shaper (110) accordingly.

公开(公告)号：US09276800B2

公开(公告)日：2016-03-01

申请号：US13608677

申请日：2012-09-10

申请人： Hyun Ho Boo ,  Seon-Ho Han ,  Jang Hong Choi ,  Ik Soo Eo ,  Hyun Kyu Yu

发明人： Hyun Ho Boo ,  Seon-Ho Han ,  Jang Hong Choi ,  Ik Soo Eo ,  Hyun Kyu Yu

IPC分类号： H04J1/02 ,  H04L27/38 ,  H04L27/20 ,  H04L27/233 ,  H04L27/36 ,  H04B1/00

CPC分类号： H04L27/3836 ,  H04B1/0007 ,  H04L27/206 ,  H04L27/2092 ,  H04L27/2332 ,  H04L27/362 ,  H04L27/3854

摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.

摘要翻译： 本发明涉及一种基于单频合成器的FDD收发器。 单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。 因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

公开(公告)号：US20140363026A1

公开(公告)日：2014-12-11

申请号：US13912905

申请日：2013-06-07

申请人： Intel IP Corporation

发明人： Chuanzhao YU ,  Mark KIRSCHENMANN

IPC分类号： G10H1/00

CPC分类号： H04L27/2092 ,  H03B28/00 ,  H03D7/12 ,  H03D7/165 ,  H04L27/0008 ,  H04L27/18 ,  H04L27/206 ,  H04L27/2071

摘要： A method of performing complementary mixing may include performing an exclusive OR (XOR) function with respect to an I-channel symbol based on an oscillator signal to produce an I-channel output signal with bits that alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling. The method may also include performing the XOR function with respect to a Q-channel symbol based on the oscillator signal to produce a Q-channel output signal with bits that alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal. Further, the method may include combining the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal.

摘要翻译： 执行互补混合的方法可以包括基于振荡器信号相对于I信道符号执行异或（XOR）功能，以产生具有在I信道符号和补码之间交替的位的I信道输出信号 的I通道符号响应于振荡器信号的上升和下降。 该方法还可以包括基于振荡器信号执行关于Q信道符号的异或函数，以产生具有在Q信道符号和Q信道符号的互补之间交替的Q信道输出信号 响应振荡器信号。 此外，该方法可以包括基于对I信道额外位信号，Q信道额外位信号，I信道输出信号执行的相加操作来组合I信道输出信号和Q信道输出信号 和Q通道输出信号，以产生互补混合信号。

公开(公告)号：US08860522B2

公开(公告)日：2014-10-14

申请号：US13125853

申请日：2008-10-24

申请人： Bengt-Erik Olsson

发明人： Bengt-Erik Olsson

IPC分类号： H04L27/12 ,  H04L27/20 ,  H04L27/00 ,  H04L27/36

CPC分类号： H04L27/0008 ,  H04L27/206 ,  H04L27/2092 ,  H04L27/2096 ,  H04L27/366

摘要： A modulator for an electrical signal comprises a data input port and a clock frequency input port. The modulator also comprises a first phase shifter for subjecting input clock frequency signals to a phase shift and adapted to keep the phase of an input clock frequency signal aligned with the phase of a data stream which is input at the data input port. The modulator also comprises a first XOR gate with an output port, to which first XOR gate said input ports of the modulator are connected, by means of which a BPSK signal is created at the output port when a first data stream is connected to the data input port and a first clock frequency signal is connected to the clock frequency input port.

摘要翻译： 用于电信号的调制器包括数据输入端口和时钟频率输入端口。 调制器还包括第一移相器，用于使输入时钟频率信号进行相移并且适于保持输入时钟频率信号的相位与在数据输入端口输入的数据流的相位对准。 所述调制器还包括具有输出端口的第一异或门，所述调制器的所述输入端口连接到所述第一异或门，当所述第一数据流连接到所述数据时，借助于所述BPSK信号在所述输出端口处产生BPSK信号 输入端口和第一个时钟频率信号连接到时钟频率输入端口。

公开(公告)号：US20140273828A1

公开(公告)日：2014-09-18

申请号：US13841155

申请日：2013-03-15

申请人： QUALCOMM INCORPORATED

发明人： Eugene Yang ,  Eunmo Kang ,  Faramarz Sabouri

IPC分类号： H04B15/00 ,  H04B5/00

CPC分类号： H04B15/00 ,  H03D3/009 ,  H03D7/165 ,  H04B5/00 ,  H04L7/033 ,  H04L25/4902 ,  H04L27/206 ,  H04L27/2092 ,  H04L2027/0018 ,  H04L2027/0057 ,  H04L2027/0067

摘要： A method for communication between near field communication (NFC) devices includes generating a transmission signal, an in-phase local oscillator signal, and a quadrature local oscillator signal from edges of an input clock signal. The method further includes mixing a load modulated signal with the in-phase local oscillator signal to generate an in-phase baseband signal. The method further includes mixing the load modulated signal with the quadrature local oscillator signal to generate a quadrature baseband signal. The method further includes adjusting a phase delay of at least one of the in-phase local oscillator signal or the quadrature local oscillator signal in response to a first signal strength of the in-phase baseband signal and a second signal strength of the quadrature baseband signal.

摘要翻译： 用于近场通信（NFC）设备之间的通信的方法包括从输入时钟信号的边缘产生发送信号，同相本地振荡器信号和正交本地振荡器信号。 该方法还包括将负载调制信号与同相本地振荡器信号混合以产生同相基带信号。 该方法还包括将负载调制信号与正交本地振荡器信号混合以产生正交基带信号。 该方法还包括响应于同相基带信号的第一信号强度和正交基带信号的第二信号强度来调整同相本地振荡器信号或正交本地振荡器信号中的至少一个的相位延迟 。

公开(公告)号：US07529534B2

公开(公告)日：2009-05-05

申请号：US11300191

申请日：2005-12-13

申请人： Stefan Koehler

发明人： Stefan Koehler

IPC分类号： H04B1/16

CPC分类号： H03H17/0621 ,  H03H17/0275 ,  H03H2017/0247 ,  H04L27/2092 ,  H04L27/2627

摘要： A signal converter for converting a start signal into an end signal includes means for copying the start signal to obtain a plurality of copied start signals, wherein a copied start signal may be fed into a processing branch as a branch signal. Further, the signal converter includes a first branch processing means in a first processing branch for processing a first branch signal according to a first processing regulation to obtain a first processed branch signal. Further, the signal converter includes a second branch processing means in a second processing branch for processing a second branch signal according to a second processing regulation to obtain a second processed branch signal, wherein the second processing regulation is different from the first processing regulation and wherein the first processing regulation and the second processing regulation are implemented to cause a low-pass polyphase filtering of the copied start signals. Finally, the signal converter includes selection means for sequentially selecting the first processed branch signal and then the second processed branch signal in order to obtain the end signal.

摘要翻译： 用于将开始信号转换为结束信号的信号转换器包括用于复制起始信号以获得多个复制的起始信号的装置，其中复制的起始信号可以作为分支信号被馈送到处理支路。 此外，信号转换器包括第一处理分支中的第一分支处理装置，用于根据第一处理调节处理第一分支信号以获得第一处理分支信号。 此外，信号转换器包括第二处理分支中的第二分支处理装置，用于根据第二处理调节处理第二分支信号以获得第二处理分支信号，其中第二处理调节与第一处理调节不同，其中 实施第一处理调节和第二处理规则以对复制的起始信号进行低通多相滤波。 最后，信号转换器包括选择装置，用于顺序地选择第一处理的分支信号，然后是第二处理的分支信号，以获得结束信号。

公开(公告)号：US07417514B2

公开(公告)日：2008-08-26

申请号：US11440343

申请日：2006-05-24

申请人： Jeff Zachan ,  David Hartman ,  Ming Lin ,  Morten Damgaard ,  Scott Kee

发明人： Jeff Zachan ,  David Hartman ,  Ming Lin ,  Morten Damgaard ,  Scott Kee

IPC分类号： H03C3/06

CPC分类号： H04L27/2092 ,  H03C3/0933 ,  H03C3/0966 ,  H03C3/0983 ,  H03L7/1976 ,  H03L2207/12 ,  H04L27/2017 ,  H04L27/2046

摘要： A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.

摘要翻译： 提供了直接分频调制器。 直接分频调制器包括将输入数据从二进制比特流转换为期望的频率偏差的符号映射器，例如频率偏差数据对来自比特流的信息进行编码的地方。 A转换器使用期望的频率偏差信息产生除法值，并且加法器将平均值加到除法值。 A转换器对分频值进行量化，并形成与量化除法相关联的量化噪声。 分频器用量化除法器调制参考信号并产生输出信号。

公开(公告)号：US20070098111A1

公开(公告)日：2007-05-03

申请号：US11261166

申请日：2005-10-27

申请人： Mark Gehring ,  Russell Moen ,  Brent Jensen

发明人： Mark Gehring ,  Russell Moen ,  Brent Jensen

IPC分类号： H04L27/12

CPC分类号： H04L27/2092

摘要： A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

摘要翻译： 发射机数字信号处理器（DSP）电路具有由查找表（LUT）输出的n位数据表示的发射频率。 n比特数据被输出到构成为以基于输出n比特数据的速率溢出的n比特累加器，以输出相位。 电路还具有被构造为向累加器添加n位有符号常数以便偏移由LUT输出的n位数据表示的频率的器件。 半导体芯片上的收发器可以包括作为发射机电路的一部分的发射DSP电路，其具有LUT，累加器和设备向累加器提供n位有符号常数以偏移发射频率，以允许接收机电路 收发器与发射机电路直接通信，从而允许对收发器进行测试。

公开(公告)号：US06724851B2

公开(公告)日：2004-04-20

申请号：US10412456

申请日：2003-04-11

申请人： David Norton Critchlow ,  Moshe Yehushua ,  Graham Martin Avis ,  Wade Lyle Heimbigner ,  Karle Joseph Johnson ,  George Alan Wiley

发明人： David Norton Critchlow ,  Moshe Yehushua ,  Graham Martin Avis ,  Wade Lyle Heimbigner ,  Karle Joseph Johnson ,  George Alan Wiley

IPC分类号： H04L2300

CPC分类号： H04L25/03343 ,  H03B28/00 ,  H03C3/00 ,  H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A FIR chip is used in a wireless subscriber unit. The subscriber unit includes a processor for transcoding an input signal to provide digital input symbols. A received output signal is demodulated. Digital output symbols are synthesized from the demodulated output signal processor and filtered digital input symbols are provided. An internal address decoder decodes to allow the processor to access internal functions of the FIR chip. A control and status register allows the processor to read the status of and control the internal functions of the FIR chip. A FIR filter filters the digital input symbols. A transmit timer controls timing which allows the processor to control the FIR filter. A receive timer generates timing signals for timing transcoding operations and synthesizing operations connected to the processor.

摘要翻译： FIR芯片用于无线用户单元。 用户单元包括用于对输入信号进行代码转换以提供数字输入符号的处理器。 接收到的输出信号被解调。 从解调输出信号处理器合成数字输出符号并提供经过滤波的数字输入符号。 内部地址解码器解码以允许处理器访问FIR芯片的内部功能。 控制和状态寄存器允许处理器读取FIR芯片的内部功能状态并控制其内部功能。 FIR滤波器对数字输入符号进行滤波。 发送定时器控制允许处理器控制FIR滤波器的定时。 接收定时器产生用于定时代码转换操作的定时信号和连接到处理器的合成操作。

公开(公告)号：US06587516B2

公开(公告)日：2003-07-01

申请号：US10223750

申请日：2002-08-20

申请人： David Norton Critchlow ,  Moshe Yehushua ,  Graham Martin Avis ,  Wade Lyle Heimbigner ,  Karle Joseph Johnson ,  George Alan Wiley

发明人： David Norton Critchlow ,  Moshe Yehushua ,  Graham Martin Avis ,  Wade Lyle Heimbigner ,  Karle Joseph Johnson ,  George Alan Wiley

IPC分类号： G06F1035

CPC分类号： H04L25/03343 ,  H03B28/00 ,  H03C3/00 ,  H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A subscriber unit has a processor. The processor provides an output phase signal corresponding to a selected output digital frequency. A tuning register buffers the phase signal. A lookup table has two sets of predefined stored values pertaining to the amplitude of a signal for a single quadrant. The predefined stored values comprise coarse angle approximations and fine angle approximations. A sine and cosine generator receives the phase signal and generates sine and cosine waveforms utilizing amplitude values obtained from the lookup table. The phase signal includes phase data and specifies the quadrant and the algebraic sign of the phase data. The sine and cosine generator accessing the lookup table differently depending upon the quadrant and sine of the phase data, such that the lookup table provides an amplitude value from the sets of predefined stored values based on the phase data. A modulator combines the sine and cosine waveforms to produce the selected output digital frequency and modulates digital frequency.