公开(公告)号：US5121392A

公开(公告)日：1992-06-09

申请号：US483168

申请日：1990-02-21

申请人： Steve Y. Sakalian

发明人： Steve Y. Sakalian

IPC分类号： H04L5/24

CPC分类号： H04L5/24

摘要： An algorithm is presented along with circuitry for implementing same to accomplish the interface of a pair of synchronized data lines with a pair of non-synchronized data lines using data buffers where there can be as few as three cells of data buffers to accomplish reading data out and writing data in without interfering one with the other. This algorithm is accomplished by measuring the time skew between overhead bits of the two non-syncrhonized data streams and writing to the frame most recently read by the synchronized data stream based on an algorithm formulated in view of or based on a function of the time skew.

摘要翻译： 呈现一种算法与电路实现相同，以使用数据缓冲器来实现一对同步数据线与一对非同步数据线的接口，其中可以存在少至三个数据缓冲器单元来完成读出数据 并且写入数据而不干扰另一个。 该算法是通过测量两个非共同化数据流的开销比特之间的时间偏差，并且基于由视觉或基于时间偏移的函数而制定的算法写入最近由同步数据流读取的帧 。

公开(公告)号：US5052025A

公开(公告)日：1991-09-24

申请号：US572740

申请日：1990-08-24

申请人： Donald G. Duff ,  Donald A. Lane ,  Ricardo Mediavilla

发明人： Donald G. Duff ,  Donald A. Lane ,  Ricardo Mediavilla

IPC分类号： H04L7/00 ,  H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04L5/24

CPC分类号： H04J3/076 ,  H04L5/24 ,  Y10S370/907

摘要： Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique adaptive bit leaking arrangement in conjunction with a digital phase locked loop and synchronizing elastic store. An estimate of a bit leaking interval is adaptively obtained based on the intervals between a sequence of consecutive pointer adjustments in the received signal, i.e., the STS-1 signal. In one embodiment, the bit leaking interval estimate is obtained by employing a moving average of the intervals between the pointer adjustments. The desired bit leaking is effected by employing an accumulator which is responsive to the received pointer adjustments and a representation of the estimated bit leaking interval, in conjunction with a comparator. The accumulator output count is supplied to the comparator along with the current write address of the elastic store. Leak bits are supplied as an output from the comparator one at a time to the phase locked loop which, in turn, generates a smooth read clock for the elastic store.

公开(公告)号：US4815099A

公开(公告)日：1989-03-21

申请号：US200112

申请日：1988-05-27

申请人： Toshimichi Shimatani ,  Yoshihiro Kawata ,  Masayuki Kawashima ,  Hideharu Omori

发明人： Toshimichi Shimatani ,  Yoshihiro Kawata ,  Masayuki Kawashima ,  Hideharu Omori

IPC分类号： H04L5/24 ,  H04J3/22

CPC分类号： H04L5/24

摘要： There is disclosed a data circuit-terminating equipment (DCE) which connects an asynchronous data terminal equipment (DTE) with a PCM trnsmission line having various speeds. Further the DCE can satisfy recomendations of the V25 bis of CCITT. The DCE includes a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make data from the DTE match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE. In the DCE satisfying the recommendations, the demapping circuit ANDs a clear-to-send signal and bits indicating the synchronized state to send the clear-to-send signal, and a short line shorting the clear-to-send signal and a carrier detect signal is employed.

摘要翻译： 公开了一种将异步数据终端设备（DTE）与具有各种速度的PCM保护线路连接的数据电路终端设备（DCE）。 此外，DCE可以满足CCITT的V25 bis的推荐。 DCE包括从线路获得时钟的PLL，产生电路定时的定时发生器，映射电路映射以使数据从DTE匹配到线速度;发送寄存器，将映射电路输出的传输速度转换为发送到 在指令期间的线路，接收寄存器，在DTE的所需期间内接收来自该线路的数据以提供所需速度的数据;以及解映射电路，接收接收寄存器输出以解映射并发送给DTE。 在满足该建议的DCE中，解映射电路对清除发送信号和指示同步状态的比特发送清除发送信号，以及短路将清除发送信号和载波检测 信号被采用。

公开(公告)号：US4635248A

公开(公告)日：1987-01-06

申请号：US700294

申请日：1985-02-11

申请人： Tadahiro Yoshida

发明人： Tadahiro Yoshida

IPC分类号： H04J3/24 ,  H04B1/66 ,  H04L5/24 ,  H04J3/00

CPC分类号： H04L5/24

摘要： Data signals in each channel over a plurality of sequential frames of a time division multiplex signal as received are temporarily stored in each channel memory, and are read out together from the channel memory at a given time to form a combined data signal. A start bit signal, a stop bit signal and an address signal corresponding to the channel are added to the combined data signal to form a start-stop synchronous fresh channel signal. The resultant N fresh channels are sequentially sent out to a common transmission line as a fresh time division multiplex signal with a reduced redundancy. A plurality of sub-equipments are connected to the common transmission line and take into the data signals of a channel assigned thereto according to the address data signal.

摘要翻译： 接收到的时分多路复用信号的多个顺序帧中的每个信道中的数据信号被临时存储在每个通道存储器中，并且在给定时间从通道存储器一起读出以形成组合的数据信号。 将起始位信号，停止位信号和对应于该通道的地址信号加到组合数据信号上以形成起始 - 停止同步新信道信号。 所得N个新鲜信道被顺序地发送到公共传输线路，作为具有减少的冗余度的新的时分多路复用信号。 多个子设备连接到公共传输线，并根据地址数据信号接收分配给它的信道的数据信号。

公开(公告)号：US3989892A

公开(公告)日：1976-11-02

申请号：US592958

申请日：1975-07-03

申请人： Shinichiro Yoshida ,  Yoshitsugu Watanabe ,  Yuji Hayano ,  Susumu Ohara ,  Takuhito Kojima

发明人： Shinichiro Yoshida ,  Yoshitsugu Watanabe ,  Yuji Hayano ,  Susumu Ohara ,  Takuhito Kojima

IPC分类号： H04Q11/04 ,  H04L5/24 ,  H04L12/52 ,  H04L5/22

CPC分类号： H04L5/24 ,  H04L12/525

摘要： A line concentrator for a time division data switching exchange. Asynchronous and synchronous data signals generated at asynchronous and synchronous data terminals are subjected to known multi-point and synchronous sampling to become a train of bit-multiplexed first asynchronous and synchronous data channel signals. Responsive to a train of bit-interleaved read-in pulse groups timed relative to the respective synchronous data signals, an arithmetic unit stores the data channel signals in an octet memory according to the asynchronous and synchronous data terminals. Responsive to a train of read-out pulses appearing for the respective data terminals, the arithmetic unit reproduces groups of uninterleaved data channel signals for each data terminal and composes the reproduced data channel signals into a train of second asynchronous and synchronous data channel signals given by a common and uninterleaved bit format. The line concentrator is readily modified for decomposition of a train of asynchronous and synchronous data channel signal groups of the bit format into replicas of the original data signals.

摘要翻译： 用于时分数据交换的线路集线器。 在异步和同步数据终端产生的异步和同步数据信号经受已知的多点和同步采样，成为一列位复用的第一异步和同步数据信道信号。 响应于相对于各个同步数据信号定时的一串比特交错读入脉冲组，算术单元根据异步和同步数据终端将数据信道信号存储在八位字节存储器中。 响应于对于各个数据终端出现的读出脉冲序列，运算单元再现每个数据终端的未交织的数据信道信号组，并将再现的数据信道信号组成由一系列第二异步和同步数据信道信号，由 一个常见的和未交织的位格式。 线集中器易于修改，用于将比特格式的异步和同步数据信道信号组的序列分解为原始数据信号的复本。

公开(公告)号：US3963871A

公开(公告)日：1976-06-15

申请号：US494701

申请日：1974-08-05

申请人： Per-Olaf Thyselius ,  Burghardt Herman Josef Vollmer ,  Knut Per Johansen

发明人： Per-Olaf Thyselius ,  Burghardt Herman Josef Vollmer ,  Knut Per Johansen

IPC分类号： H04L5/22 ,  H04L5/24 ,  H04L12/52 ,  H04L25/06 ,  H04L25/40 ,  H04J3/02 ,  H04B1/16

CPC分类号： H04L5/24 ,  H04L12/52 ,  H04L25/068 ,  H04L25/40 ,  H04L5/22

摘要： The present invention relates to an analysis device, for use in a transit exchange for transmission of asynchronous data signals with known character structure and known nominal signalling rate. The character structure comprises a start pulse and a number of data pulses which are sampled in the exchange by means of sampling pulses in synchronism with clock pulses from a clock pulse source several times per data pulse for the establishment of the binary informational content of the data signals. The device includes means through the aid of which a summation is made of the clock pulse occurring during a data pulse with indication signals being delivered at specific clock pulse positions within the data pulse. Means are further included for the summation of sampling pulses with a given binary value, thereby excluding sampling pulses occurring during the initial and final phases of a data pulse and for delivering an indication signal when a specific sum has been reached, and for the generation of a binary signal to indicate the binary value of the data pulse in correspondence to whether said specific sum has or has not been reached.

摘要翻译： 本发明涉及一种分析装置，用于在具有已知字符结构和已知标称信令速率的异步数据信号的传输交换中使用。 字符结构包括起始脉冲和多个数据脉冲，其通过采样脉冲与来自时钟脉冲源的时钟脉冲同步的每个数据脉冲多次采样脉冲进行采样，以建立数据的二进制信息内容 信号。 该装置包括借助于这些装置，其中在数据脉冲期间发生的时钟脉冲相加，其中指示信号在数据脉冲内的特定时钟脉冲位置传送。 进一步包括用于给定二进制值的采样脉冲的求和的装置，从而排除在数据脉冲的初始和最后相位期间发生的采样脉冲，并且当达到特定和时传送指示信号，并且为了产生 指示与所述特定和是否已经达到的数据脉冲的二进制值的二进制信号。

公开(公告)号：US3937882A

公开(公告)日：1976-02-10

申请号：US460179

申请日：1974-04-11

申请人： John A. C. Bingham

发明人： John A. C. Bingham

IPC分类号： H04L5/14 ,  H04L5/24 ,  H04L27/00 ,  H04L27/20 ,  H04M11/00

CPC分类号： H04L5/24 ,  H04L27/2071 ,  H04L5/143

摘要： The disclosed full-duplex communication system includes a pair of full-duplex modems, one at each end of a two wire circuit. Each of the modems includes a transmitter for transmitting over the two wire circuit a stream of synchronous data at a first carrier frequency, and a receiver for receiving over the two wire circuit a stream of synchronous data at a second carrier frequency. The receiver includes means for coherently demodulating the stream of synchronous data. In a preferred embodiment, an asynchronous-to-synchronous converter converts asynchronous input data into a stream of synchronous data for transmission by the transmitter. Also, the preferred embodiment transmits the data and receives the data as double side band suppressed carrier quadrature amplitude modulation. The system includes a remote test capability for automatically looping back test data for comparison with the transmitted test data.

公开(公告)号：US3851099A

公开(公告)日：1974-11-26

申请号：US38441473

申请日：1973-08-01

申请人： SIEMENS AG

发明人： REISINGER K

IPC分类号： H04L5/24 ,  H04J3/04

CPC分类号： H04L5/24

摘要： A circuit arrangement for the transmission of a plurality of binary coded messages and continuous signals over a common channel according to time division multiplex principles is described. A fixed character frame is used, and the characters and continuous signals are rested character by character. Prior to transmission, start and stop signals are separated from the message signal, and they are reinserted at the receiver. Message signals and continuous signals are routed to a first shift register. A start signal identifying circuit operates in response to the presence of a start signal in the first shift register to reset a code counter which records the signal elements of a message signal and restores a phase correcting circuit to its original position. The output signal from the first shift register is applied to a second shift register which has a number of stages corresponding to the number of signal elements in a message signal. The outputs of shift register stages containing information bits are connected in parallel to inputs of stages of a third shift register. The latter shift register contains a further stage for receiving the output of an evaluating circuit which interprets the states of the first and last stages of the second shift register so as to distinguish message signals from continuous signals. The parallel transmission of information signals from the second to the third shift register occurs if the first stage of the second shift register contains a start signal, the code counter has reached its final registration position and the third shift register is not currently being read out. When the multiplexer samples the channel in question, the contents of the third shift register are read out for transmission.

摘要翻译： 描述了根据时分复用原理在公共信道上传输多个二进制编码消息和连续信号的电路装置。 使用固定的字符帧，字符和连续信号逐个放置。 在传输之前，启动和停止信号与消息信号分离，并将它们重新插入接收器。 消息信号和连续信号被路由到第一移位寄存器。 启动信号识别电路响应于在第一移位寄存器中的起始信号的存在来操作，以复位记录消息信号的信号元素的代码计数器，并将相位校正电路恢复到其初始位置。 来自第一移位寄存器的输出信号被施加到第二移位寄存器，该移位寄存器具有与消息信号中的信号元素的数量相对应的级数。 包含信息位的移位寄存器级的输出与第三移位寄存器的级的输入并联连接。 后一个移位寄存器包括用于接收评估电路的输出的另一个阶段，该评估电路解释第二移位寄存器的第一和最后级的状态，以便区分消息信号与连续信号。 如果第二移位寄存器的第一级包含起始信号，代码计数器已经达到其最终注册位置，并且第三移位寄存器当前未被读出，则发生来自第二移位寄存器到第三移位寄存器的信息信号的并行传输。 当多路复用器对所述信道进行采样时，读出​​第三移位寄存器的内容进行传输。

公开(公告)号：US3754098A

公开(公告)日：1973-08-21

申请号：US3754098D

申请日：1971-10-08

申请人： ADAPTIVE TECH

发明人： ABRAMSON C ,  JONES D

IPC分类号： H04L5/24 ,  H04L25/05 ,  H04J3/06

CPC分类号： H04L5/24 ,  H04L25/05

摘要： A system and method for deriving a decoding rate to be used by a periodic decoder in reconstructing an analog or voice waveform from asynchronously received sample data that was generated at an unknown and possibly changing periodic encoding rate. Sample data representing a particular defining characteristic of a waveform at unknown but substantially uniformly spaced times is received asynchronously at a generally non-uniform rate. The sample data is stored in a buffer memory until used by a periodic decoder to reconstruct the waveform. The rate at which the periodic decoder uses samples to reconstruct the waveform is adjusted in accordance with the number of samples stored in the buffer such that the number of stored samples tends toward a median number.

摘要翻译： 一种用于导出周期性解码器使用的解码速率的系统和方法，用于以未知且可能改变的周期性编码速率生成的异步接收的采样数据重构模拟或语音波形。 以未知但基本均匀间隔的时间表示波形的特定定义特性的采样数据以非常均匀的速率异步地接收。 样本数据存储在缓冲存储器中，直到由周期性解码器用来重建波形。 根据存储在缓冲器中的样本数量来调整周期性解码器使用采样来重建波形的速率，使得存储的样本数趋向于中间数。

公开(公告)号：US3395250A

公开(公告)日：1968-07-30

申请号：US57451866

申请日：1966-07-12

申请人： WESTERN ELECTRIC CO

发明人： LIEN DALLAS H

IPC分类号： H04J3/06 ,  H04L5/24

CPC分类号： H04L5/24 ,  H04J3/0626