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    System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
    1.
    发明授权
    System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
    用于在多层全图互连架构中提供集群范围的系统时钟的系统

    公开(公告)号：US07827428B2

    公开(公告)日：2010-11-02

    申请号：US11848440

    申请日：2007-08-31

    申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G06F1/12 ,  H04J3/0685 ,  H04Q2213/13092 ,  H04Q2213/13214 ,  H04Q2213/13322 ,  H04Q2213/1336

    摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

    摘要翻译： 提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

    Method and apparatus for managing network synchronization information among multiple line cards
    2.
    发明申请
    Method and apparatus for managing network synchronization information among multiple line cards 有权
    用于管理多个线路卡之间的网络同步信息的方法和装置

    公开(公告)号：US20090119535A1

    公开(公告)日：2009-05-07

    申请号：US12283048

    申请日：2008-09-09

    申请人： Adrian Grah ,  Steven G. Driediger ,  John S. Gryba ,  Michel Rochon

    发明人： Adrian Grah ,  Steven G. Driediger ,  John S. Gryba ,  Michel Rochon

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10 ,  H04J3/0688 ,  H04Q2213/13003 ,  H04Q2213/13167 ,  H04Q2213/13214 ,  H04Q2213/1332 ,  H04Q2213/1336

    摘要： A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be applied to a redundant pair of line card circuits, where one line card circuit is active, while the other is inactive. Line card activity latches are managed by means of hardware logic that may be configured at the time of line card commissioning. The activity latches are coupled to a logic element. An incoming clock signal is applied to the logic element. If an activity latch indicates that a line card circuit is active, the logic element provides the incoming clock signal as an outgoing clock signal to a control card circuit. If the activity latch indicates that the line card circuit is inactive, the logic element blocks the incoming clock signal from being passed and provides a static output level as the outgoing clock signal to the control card circuit. The control card circuit is provided with circuitry to receive the outgoing clock signals from multiple line card circuits. The circuitry is sensitive to whether or not the line card circuits are configured for redundant operation. One or more of these clock signals are then selected and used for network synchronization.

    摘要翻译： 描述了一种用于处理，维护和控制从多个线路卡电路发出的网络同步信息的方法和装置。 所描述的技术可以应用于一对线路卡电路，其中一个线路卡电路是活动的，而另一个线路卡电路是不活动的。 线卡活动锁存器通过可在线路卡调试时配置的硬件逻辑来管理。 活动锁存器耦合到逻辑元件。 输入时钟信号被施加到逻辑元件。 如果活动锁存器指示线卡电路是有效的，则逻辑元件将输入时钟信号作为输出时钟信号提供给控制卡电路。 如果活动锁存器指示线路卡电路不活动，则逻辑元件阻止输入时钟信号被传递，并且将作为输出时钟信号的静态输出电平提供给控制卡电路。 控制卡电路设置有用于从多个线路卡电路接收输出时钟信号的电路。 电路对线卡电路是否配置为冗余操作非常敏感。 然后选择这些时钟信号中的一个或多个，并用于网络同步。

    Transport of DTMF tones over VOATM/VOIP networks
    3.
    发明授权
    Transport of DTMF tones over VOATM/VOIP networks 有权
    通过VOATM / VOIP网络传输DTMF音

    公开(公告)号：US07486665B2

    公开(公告)日：2009-02-03

    申请号：US10994559

    申请日：2004-11-22

    申请人： Anantha R. Mekala ,  Subrahmanyam V. Kunapuli ,  Jason A. Kuhne ,  Salman Haider

    发明人： Anantha R. Mekala ,  Subrahmanyam V. Kunapuli ,  Jason A. Kuhne ,  Salman Haider

    IPC分类号： H04L12/66 ,  H04J3/12

    CPC分类号： H04Q11/04 ,  H04L12/66 ,  H04L65/1026 ,  H04L65/103 ,  H04M7/1295 ,  H04Q2213/13034 ,  H04Q2213/13196 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/1329 ,  H04Q2213/13296 ,  H04Q2213/13389 ,  H04Q2213/13405

    摘要： A communication device, such as a Voice over Internet Protocol (VoIP) gateway, determines a duration for Dual Tone Multi-Frequency (DTMF) tone portions of telephony signal. If the duration is less than a pre-determined amount, a minimum duration is enforced during DTMF playback at a remote end of a network connection connected to a destination gateway. Minimum playback duration can be enforced at the terminating gateway—however, the originatinggateway can also encode a DTMF packet with a minimum duration value. At the terminating receiver it is not always possible to playback exactly what happened at the originating point in the same time frame. One solution to is to, at the terminating gateway, drop the first portion of voice packets that overlap with the end portion of played back DTMF tones.

    摘要翻译： 通信设备，例如因特网协议语音（VoIP）网关，确定电话信号的双音多频（DTMF）音部分的持续时间。 如果持续时间小于预定的量，则在连接到目的地网关的网络连接的远程端的DTMF回放期间执行最小持续时间。 最终重放持续时间可以在终端网关上实施 - 然而，发起端口也可以对具有最小持续时间值的DTMF分组进行编码。 在终端接收机处，并不总是可以在同一时间帧内准确地回放起始点发生的事件。 一种解决方案是在终端网关处丢弃与回放DTMF音调的末端部分重叠的语音分组的第一部分。

    Method and system for distributing a timing signal
    6.
    发明授权
    Method and system for distributing a timing signal 失效
    用于分配定时信号的方法和系统

    公开(公告)号：US06909701B1

    公开(公告)日：2005-06-21

    申请号：US09541387

    申请日：2000-03-31

    申请人： Ioan V. Teodorescu

    发明人： Ioan V. Teodorescu

    IPC分类号： H04J3/06 ,  H04Q11/00

    CPC分类号： H04J3/0688 ,  H04Q2213/13213 ,  H04Q2213/13214 ,  H04Q2213/13299

    摘要： A system for distributing a timing signal is disclosed. A timing generator inserts a phase of a timing signal and a command signal into a framed signal. A distribution module receives the framed signal from the timing generator. A bus control module receives the framed signal from the distribution module and distributes the framed signal to a telecommunication system. A method for distributing a timing signal in a telecommunication system is disclosed. A phase of a timing signal and a command signal is inserted into a framed signal using a timing generator. The framed signal is transmitted to a distribution module. The framed signal is transmitted to a bus control module. The framed signal is distributed to a telecommunication system using the bus control module.

    摘要翻译： 公开了一种用于分配定时信号的系统。 定时发生器将定时信号和命令信号的相位插入成帧信号。 分配模块从定时发生器接收成帧信号。 总线控制模块从分配模块接收成帧信号，并将成帧信号分配给电信系统。 公开了一种用于在电信系统中分配定时信号的方法。 使用定时发生器将定时信号和指令信号的相位插入成帧信号。 成帧信号被传送到分配模块。 成帧信号被传送到总线控制模块。 帧信号使用总线控制模块分配到电信系统。

    Extended distribution of ADSL signals
    7.
    发明授权
    Extended distribution of ADSL signals 失效
    ADSL信号扩展分布

    公开(公告)号：US06886181B1

    公开(公告)日：2005-04-26

    申请号：US09612445

    申请日：2000-07-07

    申请人： David E. Dodds ,  Oliver Cruder ,  Mark Labbe

    发明人： David E. Dodds ,  Oliver Cruder ,  Mark Labbe

    IPC分类号： H04L25/49 ,  H04Q11/04 ,  H04N7/173

    CPC分类号： H04L25/4908 ,  H04Q11/04 ,  H04Q2213/1301 ,  H04Q2213/13034 ,  H04Q2213/13039 ,  H04Q2213/1305 ,  H04Q2213/1309 ,  H04Q2213/13099 ,  H04Q2213/1319 ,  H04Q2213/13214 ,  H04Q2213/13291 ,  H04Q2213/13292 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/13332 ,  H04Q2213/1336

    摘要： A plurality of metallic telephone lines carrying both baseband POTS (plain old telephone service) and DSL (digital subscriber line) or ADSL (asymmetric digital subscriber line) signals originate at customer premises and pass through a common field cabinet enroute to a telephone central office. Baseband POTS signals flow in an undisturbed manner through the field cabinet and maintain the normal, highly reliable, communication between the subscriber premises and the central office telephone switch. At the field cabinet, DSL/ADSL signals are removed from the metallic telephone line and are then communicated between the field cabinet and the central office using fiber optic broadband transmission. Fiber optic transmission increases the allowed distance between the ADSL transceiver located at the customer location and the respective ADSL transceiver located in the telephone central office. In the optical fiber, DSL and ADSL signals are retained in their 2B1Q, DMT, QAM or CAP analog format and are simply frequency translated in the process of frequency division multiplex (FDM) transmission. The arrangement allows the provision of ADSL service to customers beyond the distance limit normally imposed by a completely metallic telephone line. It is understood that this arrangement is equally applicable to a variety of DSL (digital subscriber line) signals.

    摘要翻译： 携带基带POTS（普通老式电话业务）和DSL（数字用户线路）或ADSL（非对称数字用户线路）信号的多条金属电话线路始发于客户驻地，并通过公共场地机柜通往电话中心局。 基带POTS信号以不受干扰的方式通过现场柜流动，并保持用户驻地与中心局电话交换机之间的正常，高度可靠的通信。 在现场机柜中，DSL / ADSL信号从金属电话线路中移除，然后使用光纤宽带传输在现场柜和中心局之间进行通信。 光纤传输增加了位于客户位置的ADSL收发器与位于电话中心局的相应ADSL收发器之间的允许距离。 在光纤中，DSL和ADSL信号保留在2B1Q，DMT，QAM或CAP模拟格式中，并且在频分复用（FDM）传输过程中简单地进行频率转换。 该安排允许向超过通常由完全金属电话线施加的距离限制的客户提供ADSL服务。 应当理解，这种布置同样适用于各种DSL（数字用户线路）信号。

    Cascaded parallel phase locked loops
    8.
    发明授权
    Cascaded parallel phase locked loops 有权
    级联并联锁相环

    公开(公告)号：US06876651B1

    公开(公告)日：2005-04-05

    申请号：US09666446

    申请日：2000-09-21

    申请人： Ossi Ilari Grohn

    发明人： Ossi Ilari Grohn

    IPC分类号： H03L7/06 ,  H04J3/06 ,  H04Q11/00

    CPC分类号： H03L7/06 ,  H04J3/0685 ,  H04Q2213/13098 ,  H04Q2213/13214 ,  H04Q2213/13322 ,  H04Q2213/1336

    摘要： A parallel cascaded set of transceivers using phase locked loops comprises a PCM communication link therebetween. At a first transceiver station, a primary framer receives an incoming signal. The primary framer extracts a payload signal and a clock signal and splits both. One clock signal is directed to the phase locked loop and the other clock signal is directed to a downstream transceiver. In this manner, start up delay and error introduction are reduced.

    摘要翻译： 使用锁相环的并联级联收发器集合包括它们之间的PCM通信链路。 在第一收发台，主成帧器接收输入信号。 主成帧器提取有效载荷信号和时钟信号，并分裂两者。 一个时钟信号指向锁相环，另一个时钟信号被引导到下游收发器。 以这种方式，减少启动延迟和错误的介绍。

    Method based on backboard transmitting time division multiplexing circuit data and a bridge connector
    9.
    发明申请
    Method based on backboard transmitting time division multiplexing circuit data and a bridge connector 有权
    基于背板传输时分复用电路数据和桥接器的方法

    公开(公告)号：US20040120351A1

    公开(公告)日：2004-06-24

    申请号：US10476407

    申请日：2003-10-29

    发明人： Zhenya Li ,  Guzheng Wu ,  Quan Yu ,  Shoubo Xie ,  Konggang Wei

    IPC分类号： H04J003/00

    CPC分类号： H04Q11/04 ,  H04Q2213/13166 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1336

    摘要： The invention discloses a method for multi-path TDM data transmission based on backplane and a TDM bridge connector for implementing the method. The method includes: applying a high-speed serial line on backplane to connect a center switch network board and service boards; multiplexing or interleaving multi-path TDM data at transmitting side, and then transmitting in batch to said high-speed serial line on the backplane; at receiving side, serial receiving said data and de-multiplexing or de-interleaving them to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity on backplane and looses the requirement of clock synchronization, so the system reliability is greatly raised.

    摘要翻译： 本发明公开了一种用于实现该方法的基于背板和TDM桥接器的多路TDM数据传输方法。 该方法包括：在背板上应用高速串行线路连接中心交换机网络板和业务板; 在发送侧多路复用或交织多路径TDM数据，然后批量传输到背板上的所述高速串行线路; 在接收侧，串行接收所述数据，并将它们解复用或解交织到多个TDM路径。 TDM桥​​接器包括：TDM高速串行传输自适应电路，TDM高速串行接收自适应电路和时钟控制电路。 本发明大大提高了背板的传输容量，不再需要时钟同步，从而大大提高了系统的可靠性。