公开(公告)号：US20180144436A1

公开(公告)日：2018-05-24

申请号：US15688837

申请日：2017-08-28

申请人： INTEL CORPORATION

发明人： Michael APODACA

IPC分类号： G06T1/20 ,  G06F1/32 ,  G06F15/76

CPC分类号： G06T1/20 ,  G06F1/3212 ,  G06F1/3265 ,  G06F1/329 ,  G06F15/76 ,  G06T2200/28 ,  Y02D10/153 ,  Y02D10/174 ,  Y02D10/24 ,  Y02D10/28 ,  Y02D10/40

摘要： Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.

公开(公告)号：US09836378B2

公开(公告)日：2017-12-05

申请号：US14964356

申请日：2015-12-09

申请人： Dell Products L.P.

发明人： Mukund Purshottam Khatri ,  Tuyet-Huong Thi Nguyen ,  Vijay Nijhawan ,  Robert Hormuth

IPC分类号： G06F9/30 ,  G06F11/34 ,  G06F9/455 ,  G06F11/30

CPC分类号： G06F11/3409 ,  G06F9/45533 ,  G06F11/301 ,  G06F11/3055 ,  G06F11/3065 ,  Y02D10/26 ,  Y02D10/28

摘要： An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

公开(公告)号：US09792135B2

公开(公告)日：2017-10-17

申请号：US14887902

申请日：2015-10-20

申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC

发明人： Ezekiel Kruglick

IPC分类号： G06F9/455 ,  G06F1/00 ,  G06F11/30 ,  G06F9/48 ,  G06F1/26

CPC分类号： G06F9/45533 ,  G06F1/26 ,  G06F9/455 ,  G06F9/48 ,  G06F9/4893 ,  G06F11/30 ,  G06F11/3062 ,  G06F2201/815 ,  Y02D10/24 ,  Y02D10/26 ,  Y02D10/28

摘要： Technologies are generally described for systems, devices and methods effective to schedule access to a core. In some examples, a first differential voltage frequency scaling (DVFS) value of a first virtual machine may be received by a virtual machine manager. A second DVFS value of a second virtual machine may be received by the virtual machine manager. A third DVFS value of a third virtual machine may be received by the virtual machine manager. The third DVFS value may be substantially the same as the first DVFS value and different from the second DVFS value. A dispatch cycle may be generated to execute the first, second and third virtual machines on the core. After execution of the first virtual machine, the dispatch cycle may require execution of the third virtual machine before execution of the second virtual machine.

公开(公告)号：US09710295B2

公开(公告)日：2017-07-18

申请号：US14112923

申请日：2012-04-18

申请人： Keisuke Yamaguchi

发明人： Keisuke Yamaguchi

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F11/14

CPC分类号： G06F9/45558 ,  G06F9/45533 ,  G06F9/5077 ,  G06F11/1484 ,  G06F2009/4557 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： In a virtual machine system, an arrangement of virtual machines, which has fault tolerance, is performed. A virtual machine managing apparatus includes a similar group generating unit and an arrangement restriction generating unit. The similar group generating unit generates a group of virtual machines having a similarity relationship which indicates that performance values of virtual machines at each timing are approximately the same, out of plural virtual machines. The arrangement restriction generating unit outputs the group of virtual machines having the similarity relationship as a distributed-arrangement restriction indicating a group of virtual machines to be arranged on different processing apparatuses among plural processing apparatuses carrying out processes of the virtual machines.

公开(公告)号：US09710047B2

公开(公告)日：2017-07-18

申请号：US14572854

申请日：2014-12-17

申请人： FUJITSU LIMITED

发明人： Masahiro Miwa

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F13/00 ,  G06F15/167 ,  G06F13/24 ,  G06F9/455 ,  G06F13/16

CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/45533 ,  G06F13/1657 ,  Y02D10/126 ,  Y02D10/26 ,  Y02D10/28

摘要： An information processing apparatus connected to another information processing apparatus includes an arithmetic processing device, and one or more processors configured to detect an exception event of a self main memory when the arithmetic processing device requests an access to data on a main memory possessed by the another information processing apparatus and vary a clock frequency or a voltage of the arithmetic processing device on the basis of the detection of the exception event.

公开(公告)号：US20160378538A1

公开(公告)日：2016-12-29

申请号：US15261615

申请日：2016-09-09

申请人： NeoDana, Inc.

发明人： Dan C. Kang

IPC分类号： G06F9/455 ,  G06F9/50 ,  H04L29/06 ,  G06F9/48

CPC分类号： G06F9/50 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/5055 ,  G06F9/5061 ,  G06F9/5077 ,  G06F9/5083 ,  G06F9/5088 ,  G06F21/53 ,  G06F21/6218 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2009/45595 ,  G06F2221/2149 ,  H04L63/0227 ,  H04L63/0428 ,  H04L63/14 ,  Y02D10/26 ,  Y02D10/28

摘要： A system and method for virtualization and cloud security are disclosed. According to one embodiment, a system comprises a first multi-core processing cluster and a second multi-core processing cluster in communication with a network interface card and software instructions. When the software instructions are executed by the second multi-core processing cluster they cause the second multi-core processing cluster to receive a request for a service, create a new or invoke an existing virtual machine to service the request, and return a desired result indicative of successful completion of the service to the first multi-core processing cluster.

公开(公告)号：US09501124B2

公开(公告)日：2016-11-22

申请号：US12125905

申请日：2008-05-22

申请人： Robert M. Fries

发明人： Robert M. Fries

IPC分类号： G06F9/455 ,  G06F1/32 ,  G06F1/20 ,  G06F9/50 ,  G06Q10/04

CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F9/45533 ,  G06F9/5088 ,  G06F9/5094 ,  G06Q10/04 ,  Y02D10/16 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/32

摘要： An optimized placement of virtual machines may be determined by optimizing an energy cost for a group of virtual machines in various configurations. For various hardware platforms, an energy cost per performance value may be determined. Based on the performance usage of a group of virtual machines, a total power cost may be determined and used for optimization. In some implementations, an optimized placement may include operating a group of virtual machines in a manner that does not exceed a total energy cost for a period of time.

摘要翻译： 可以通过以各种配置优化一组虚拟机的能量成本来确定虚拟机的优化布局。 对于各种硬件平台，可以确定每个性能值的能量成本。 基于一组虚拟机的性能使用，可以确定总功率成本并用于优化。 在一些实现中，优化的放置可以包括在一段时间内以不超过总能量成本的方式操作一组虚拟机。

公开(公告)号：US09383811B2

公开(公告)日：2016-07-05

申请号：US13301358

申请日：2011-11-21

申请人： Teng-Chang Chang

发明人： Teng-Chang Chang

IPC分类号： G06F13/14 ,  G06F1/32 ,  G06F9/455

CPC分类号： G06F1/3293 ,  G06F9/45533 ,  Y02D10/122 ,  Y02D10/26 ,  Y02D10/28

摘要： A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

摘要翻译： 一种用于异构计算机系统的桥逻辑装置，其具有至少一个性能处理器，支持逻辑的支持所述至少一个性能处理器来执行所述软件的任务的处理器，以及消耗比所述至少一个性能处理器更少的功率的管理程序处理器 披露 所述桥逻辑设备包括管理程序操作逻辑，其维护所述系统在所述至少一个性能处理器下的状态; 处理器语言翻译器逻辑，其在所述至少一个性能的处理器语言和所述管理程序处理器之间进行转换; 以及具有第一，第二和第三端口的高速总线开关，用于双向地跨过三个端口中的任一个端口中继数据。 该交换机经由处理器语言翻译器逻辑连接至该至少一个性能处理器，该管理程序处理器，以及分别在第一，第二和第三端口处的处理器支持逻辑。

公开(公告)号：US09378018B2

公开(公告)日：2016-06-28

申请号：US14828131

申请日：2015-08-17

申请人： MicroUnity Systems Engineering, Inc.

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/00

CPC分类号： G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

摘要翻译： 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明提供了通过使用通用寄存器的内容来实质上大于处理器的数据路径的操作数，以指定可读取或写入数据的多个数据路径宽度的存储器地址，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

公开(公告)号：US09274822B2

公开(公告)日：2016-03-01

申请号：US14238470

申请日：2013-04-30

申请人： Empire Technology Development LLC

发明人： Ezekiel Kruglick

IPC分类号： G06F9/46 ,  G06F15/173 ,  G06F9/445 ,  G06F9/455 ,  G06F11/30 ,  H04L12/26 ,  H04L12/911

CPC分类号： G06F9/45533 ,  G06F8/60 ,  G06F8/65 ,  G06F9/45558 ,  G06F11/3006 ,  G06F11/3062 ,  G06F11/3433 ,  G06F11/3452 ,  G06F2201/815 ,  H04L43/08 ,  H04L47/70 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/34

摘要： Technologies are generally provided for reactive loop sensing in multi-datacenter deployments. In some examples, tagged metrics from deployment elements on different datacenter or platform providers may be used by a stability module to generate a synthetic generalized deployment model that aliases multiple system elements into general state vectors. The state vectors may include a transfer vector on the border between each datacenter or platform, and the feedback from the metrics may cause the states of the datacenters/platforms to match the deployment's unobserved variables allowing stability analysis before failure. For example, the metrics may be associated with a portion of the deployment on one of the multiple datacenters. The stability analysis module may compare the received metrics with model metrics derived from a model of the multi-datacenter deployment to determine the stability of the deployment and/or adjust the model for increased stability.

摘要翻译： 通常为多数据中心部署中的反应环路检测提供技术。 在一些示例中，稳定性模块可以使用来自不同数据中心或平台提供商上的部署元素的标记度量来生成将多个系统元素设为通用状态向量的合成广义部署模型。 状态向量可以包括在每个数据中心或平台之间的边界上的传输向量，并且来自度量的反馈可以导致数据中心/平台的状态与部署的未观察到的变量匹配，从而允许在故障之前进行稳定性分析。 例如，度量可以与多个数据中心之一上的部署部分相关联。 稳定性分析模块可以将接收到的度量与来自多数据中心部署模型的模型度量进行比较，以确定部署的稳定性和/或调整模型以增加稳定性。