公开(公告)号：US5587597A

公开(公告)日：1996-12-24

申请号：US728917

申请日：1991-07-11

申请人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

发明人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

IPC分类号： H01L21/768 ,  H01L21/86 ,  H01L23/482 ,  H01L27/12 ,  H01L29/04 ,  H01L31/0392 ,  H01L31/062

CPC分类号： H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

摘要： A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

摘要翻译： 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

公开(公告)号：US5580806A

公开(公告)日：1996-12-03

申请号：US369727

申请日：1995-01-06

申请人： Tsun-Tsai Chang ,  Ming-Tsung Liu

发明人： Tsun-Tsai Chang ,  Ming-Tsung Liu

IPC分类号： H01L21/8244 ,  H01L21/441

CPC分类号： H01L27/11 ,  Y10S148/019

摘要： A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect layer. A silicide layer is formed on the sidewall of the interconnect layer. The silicide layer connects a buried contact region with the interconnect layer to make electrical contact between the interconnect layer and a source/drain region.

摘要翻译： 形成在半导体衬底上的埋入接触结构。 在场氧化物层上形成单个多晶硅层。 对多晶硅层进行图案化和蚀刻以形成互连层。 在互连层的侧壁上形成硅化物层。 硅化物层将掩埋接触区域与互连层连接，以在互连层和源极/漏极区域之间形成电接触。

公开(公告)号：US5541455A

公开(公告)日：1996-07-30

申请号：US393709

申请日：1995-02-24

申请人： Robert L. Hodges

发明人： Robert L. Hodges

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/94

CPC分类号： H01L27/11 ,  H01L21/28525 ,  H01L21/76889 ,  Y10S148/019

摘要： A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi.sub.2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.

公开(公告)号：US5512516A

公开(公告)日：1996-04-30

申请号：US315576

申请日：1994-09-30

申请人： Kenji Nishida ,  Noriaki Sato

发明人： Kenji Nishida ,  Noriaki Sato

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L23/532 ,  H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L23/485 ,  H01L23/53257 ,  H01L29/665 ,  H01L2924/0002 ,  Y10S148/019

摘要： A contact structure for connecting a semiconductor device to a wiring electrode includes a semiconductor layer forming a part of the semiconductor device. A first contact layer of reduced resistivity covers a surface of the semiconductor layer. An insulating structure is provided on the first contact layer so as to bury the first contact layer underneath. A penetrating hole is opened through the insulating structure so as to expose a part of the first contact layer. A second contact layer of reduced resistivity is provided on the part of the first contact layer exposed by the penetrating hole. The second contact layer extends from a bottom of the penetrating hole along its side wall. A conductor layer forms the wiring electrode on the second contact layer.

摘要翻译： 用于将半导体器件连接到布线电极的接触结构包括形成半导体器件的一部分的半导体层。 具有降低电阻率的第一接触层覆盖半导体层的表面。 在第一接触层上设置绝缘结构，以将第一接触层埋在下面。 通过绝缘结构打开穿透孔，以露出第一接触层的一部分。 在由穿透孔暴露的第一接触层的部分上设置电阻率降低的第二接触层。 第二接触层沿其侧壁从穿透孔的底部延伸。 导体层在第二接触层上形成布线电极。

公开(公告)号：USRE35111E

公开(公告)日：1995-12-05

申请号：US984084

申请日：1992-11-30

申请人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02

摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the rust metal silicide layer from damage.

摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护防锈金属硅化物层免受损坏。

公开(公告)号：US5418179A

公开(公告)日：1995-05-23

申请号：US291728

申请日：1994-08-16

申请人： Tadahiko Hotta

发明人： Tadahiko Hotta

IPC分类号： H01L21/768 ,  H01L21/70

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  Y10S148/019 ,  Y10S148/147

摘要： An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

摘要翻译： 集成电路制造在半导体衬底上，并且包括n沟道型场效应晶体管，ap沟道型场效应晶体管和耦合在两个场效应晶体管的漏极区之间的互连，并且每个栅电极和互连是 设置有沉积在多晶硅上的多晶硅和难熔金属硅化物，其中从栅电极和互连中去除侧间隔物，因为通过沉积在栅电极和源极和漏极区之间不发生短路 的难熔金属硅化物。

公开(公告)号：US5365111A

公开(公告)日：1994-11-15

申请号：US995869

申请日：1992-12-23

申请人： Seshadri Ramaswami ,  Robin W. Cheung

发明人： Seshadri Ramaswami ,  Robin W. Cheung

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/45 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L21/76889 ,  H01L23/53257 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S148/019

摘要： A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned. The second heating step, which is at a higher temperature than the first, converts all the titanium silicides to titanium disilicide.

摘要翻译： 用于将硅区域（16）连接到由氧化物区域（24）分开的硅区域（20）的局部互连硅化物结构（30）包括与硅区域接触的钛硅化物/氮化钛/硅化钛的第一部分和第二部分 钛/氮化钛/硅化钛与氧化物区域接触。 硅化物结构也可用于连接源/漏区（14）和多晶硅互连（28）。 采用两个单独的加热步骤，通过蚀刻步骤分离以形成互连（34,36）。 第一加热步骤使用第一钛层（30a）在硅化物结构的底部形成（a）具有单个或多晶硅的硅化钛，和（b）具有非晶硅（30d）的硅化钛，使用第二钛层 30c）在其上沉积非晶硅的氮化钛层（30b）的顶部上，然后构图。 在比第一加热步骤高的第二加热步骤将所有的钛硅化物转化成二硅化钛。

公开(公告)号：US5336637A

公开(公告)日：1994-08-09

申请号：US082139

申请日：1993-06-24

申请人： Edward J. Nowak

发明人： Edward J. Nowak

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/02 ,  H01L29/80

CPC分类号： H01L27/0925 ,  Y10S148/019 ,  Y10S148/103

摘要： In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

摘要翻译： 在半导体器件中，形成在衬底上的差分掺杂扩散区域的互连包括设置在两个扩散区域之间的互连层，使得两个区域彼此耦合。 互连区域由N +掺杂剂和P +掺杂剂区域的现有掩模边界限定，使得N +和P +掺杂剂不允许进入互连区域。 因此，限定互连区域而不需要额外的掩模和蚀刻步骤。 一旦定义了互连区域，则通过沉积和烧结工艺形成互连层。 互连层提供肖特基势垒和欧姆接触。

公开(公告)号：US5326724A

公开(公告)日：1994-07-05

申请号：US815312

申请日：1991-12-27

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/28518 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S438/902 ,  Y10S438/97

摘要： A titanium nitride layer is deposited between the metal titanium layer and the oxide cap of a conventional oxide capped titanium disilicide technology process. This titanium nitride layer is deposited in-situ after a certain thickness of metal titanium has been deposited by bleeding nitrogen gas into the titanium sputter machine. Thereafter the normal oxide cap is deposited over this titanium nitride layer. The normal titanium react process is performed to produce titanium disilicide. After the titanium disilicide has been produced, it is then necessary to strip off the oxide cap. The extra titanium nitride layer makes it is possible to use a wet etch to remove the oxide cap, with the titanium nitride layer serving as a etch stop. In this manner an isotropic wet etch may be employed to remove all of the oxide cap layer. The isotropic wet etch is preferably a 10% buffered HF etch.

摘要翻译： 在常规氧化物封端的二硅化钛工艺工艺的金属钛层和氧化物盖之间沉积氮化钛层。 在通过将氮气渗入钛溅射机中沉积了一定厚度的金属钛之后，该氮化钛层原位沉积。 此后，在该氮化钛层上沉积正常氧化物盖。 进行正常的钛反应工艺以生产二硅化钛。 在制造二硅化钛后，需要剥离氧化物盖。 额外的氮化钛层使得可以使用湿蚀刻去除氧化物盖，其中氮化钛层用作蚀刻停止。 以这种方式，可以采用各向同性的湿蚀刻来去除所有氧化物盖层。 各向同性湿蚀刻优选为10％缓冲的HF蚀刻。

公开(公告)号：US5206187A

公开(公告)日：1993-04-27

申请号：US812063

申请日：1991-12-17

申请人： Trung T. Doan ,  Gurtej S. Sandhu

发明人： Trung T. Doan ,  Gurtej S. Sandhu

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31111 ,  H01L21/76802 ,  Y10S148/019 ,  Y10S438/97

摘要： A method of processing a semiconductor wafer comprises: a) fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations of the wafer; b) providing a layer of transition metal oxide elevationally above the active regions; c) applying an insulating dielectric layer elevationally above the transition metal oxide layer; d) etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and e) etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.

摘要翻译： 一种处理半导体晶片的方法包括：a）制造晶片以限定多个导电掺杂的有源区，所述有源区具有位于所述晶片的不同高度的向外暴露的表面; b）在活性区上方提供过渡金属氧化物层; c）在所述过渡金属氧化物层的上方施加绝缘介电层; d）使用对过渡金属氧化物具有高选择性的蚀刻化学品蚀刻绝缘介电层的选定部分，并使用过渡金属氧化物作为有效蚀刻停止，使得能够在单个蚀刻中蚀刻绝缘介电层 步进到处于不同高度的相邻选定的有效区域; 以及e）从所选择的部分蚀刻过渡金属氧化物并向上暴露所选择的活性区域。