公开(公告)号：US6093620A

公开(公告)日：2000-07-25

申请号：US396733

申请日：1989-08-18

申请人： Douglas L. Peltzer

发明人： Douglas L. Peltzer

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/32 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/8605

CPC分类号： H01L21/32 ,  H01L21/033 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/0635 ,  H01L29/0821 ,  H01L29/8605 ,  Y10S148/03 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/145

摘要： A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

摘要翻译： 形成在硅衬底上的薄硅外延层通过延伸穿过外延层的横向延伸的PN结的外延硅材料的氧化区的栅格细分为电隔离的穴。

公开(公告)号：US5889315A

公开(公告)日：1999-03-30

申请号：US393622

申请日：1995-02-23

申请人： Douglas R. Farrenkopf ,  Richard B. Merrill ,  Samar Saha ,  Kevin E. Brehmer ,  Kamesh Gadepally ,  Philip J. Cacharelis

发明人： Douglas R. Farrenkopf ,  Richard B. Merrill ,  Samar Saha ,  Kevin E. Brehmer ,  Kamesh Gadepally ,  Philip J. Cacharelis

IPC分类号： H01L21/761 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/00

CPC分类号： H01L21/761 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/0203 ,  Y10S148/085

摘要： Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

摘要翻译： 适合于高性能应用的集成电路，特别是具有模拟和数字部分的混合信号产品，可从具有两级埋入区域的半导体结构制造。 在典型的实施例中，相反导电类型的较低掩埋区域沿着半导体衬底和上覆下半导体层之间的下半导体界面设置。 相反导电类型的上掩埋区类似地位于下半导体层和上半导电层之间的上半导体界面处。 上半导体层包含晶体管区所在的P型和N型器件区。 半导体结构通常被配置为使得每个P型和N型器件区域中的至少一个与衬底电隔离。 互补双极晶体管可以与结构中的互补场效应晶体管集成。

公开(公告)号：US5751054A

公开(公告)日：1998-05-12

申请号：US705910

申请日：1996-08-29

申请人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun Wei Chen

发明人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun Wei Chen

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L29/861 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085

摘要： A semiconductor structure which includes zener diodes and various combinations of MOS transistors, bipolar transistors and DMOS transistors, all fabricated on the same integrated circuit chip

摘要翻译： 包括齐纳二极管和MOS晶体管，双极晶体管和DMOS晶体管的各种组合的半导体结构，全部制造在相同的集成电路芯片

公开(公告)号：US5536665A

公开(公告)日：1996-07-16

申请号：US442928

申请日：1995-05-17

申请人： Shigeki Komori ,  Takashi Kuroi ,  Masahide Inuishi

发明人： Shigeki Komori ,  Takashi Kuroi ,  Masahide Inuishi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L21/266

CPC分类号： H01L27/0921 ,  H01L27/10805 ,  Y10S148/085

摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

摘要翻译： 半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱 。 在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。 根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。 结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

公开(公告)号：US5485027A

公开(公告)日：1996-01-16

申请号：US904402

申请日：1992-06-24

申请人： Richard K. Williams ,  Richard A. Blanchard

发明人： Richard K. Williams ,  Richard A. Blanchard

IPC分类号： H01L21/336 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L29/66712 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/1083 ,  H01L29/7809 ,  H01L29/7835 ,  H01L27/088 ,  H01L29/1095 ,  Y10S148/085

摘要： In an integrated circuit, a wraparound isolation region capable of sustaining a high blocking voltage to a substrate encloses a variety of high voltage or low voltage device.

摘要翻译： 在集成电路中，能够对基板维持高阻断电压的环绕隔离区包围各种高压或低电压器件。

公开(公告)号：US5426328A

公开(公告)日：1995-06-20

申请号：US226419

申请日：1994-04-11

申请人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

发明人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L29/861 ,  H01L29/70 ,  H01L27/102 ,  H01L29/73

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085

摘要： A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种同时形成高质量互补双极晶体管，相对高电压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器或这些的任何期望组合的方法，全部在同一集成电路芯片上 。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5422508A

公开(公告)日：1995-06-06

申请号：US26930

申请日：1993-03-05

申请人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

发明人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L29/861 ,  H01L29/772 ,  H01L29/70 ,  H01L29/73

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085

摘要： A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种同时形成高质量互补双极晶体管，相对高电压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器或这些的任何期望组合的方法，全部在同一集成电路芯片上 。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5344785A

公开(公告)日：1994-09-06

申请号：US72653

申请日：1993-06-03

申请人： Rick C. Jerome ,  Diane R. Williams ,  Kurt D. Humphrey

发明人： Rick C. Jerome ,  Diane R. Williams ,  Kurt D. Humphrey

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L27/082 ,  H01L21/265

CPC分类号： H01L29/66265 ,  H01L21/76235 ,  H01L27/082 ,  Y10S148/085 ,  Y10S148/15

摘要： A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.

摘要翻译： 在硅绝缘体（“SOI”）集成电路（“IC”）中制造各种类型的硅器件（例如互补双极性PNP和NPN晶体管）的方法，具有衬底的SOI IC，设置在上面的掩埋绝缘层 衬底和设置在绝缘层上方的硅器件层。 可以在器件层中形成垂直晶体管，使得每个晶体管完全介电地与另一晶体管隔离，也可以与硅器件层中的其它类似制造的硅器件完全介电隔离。

公开(公告)号：US5294559A

公开(公告)日：1994-03-15

申请号：US559756

申请日：1990-07-30

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76297 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/7802 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/0847 ,  Y10S148/085 ,  Y10S148/135

摘要： A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.

摘要翻译： 垂直晶体管包括具有形成在其中的第一掺杂区域（48）的第一导电类型的半导体层。 第二掺杂区域（50）形成在第一掺杂区域（48）内。 栅极覆盖第一掺杂区域，使得可以响应于施加到栅极的电压而产生第二掺杂区域和半导体层之间的低阻抗路径。 通过半导体层形成绝缘区域（38和58），以将晶体管与其它器件隔离。

公开(公告)号：US5156989A

公开(公告)日：1992-10-20

申请号：US268839

申请日：1988-11-08

申请人： Richard K. Williams ,  Richard A. Blanchard

发明人： Richard K. Williams ,  Richard A. Blanchard

IPC分类号： H01L21/336 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/1083 ,  H01L29/7809 ,  H01L29/7835 ,  H01L27/088 ,  H01L29/1095 ,  Y10S148/085

摘要： A process sequence that produces a plurality of pretransistor structures from which a variety of high voltage, isolated integrated circuits and low voltage integrated circuits are easily fabricated.

摘要翻译： 产生多个预晶体管结构的工艺序列，从其容易地制造各种高压隔离集成电路和低压集成电路。