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公开(公告)号：US07911012B2
公开(公告)日：2011-03-22
申请号：US12009581
申请日：2008-01-18
Applicant: Glenn Leedy
Inventor： Glenn Leedy
IPC: G01L9/00
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。
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公开(公告)号：US07670893B2
公开(公告)日：2010-03-02
申请号：US10700429
申请日：2003-11-03
Applicant: Glenn J Leedy
Inventor： Glenn J Leedy
IPC: H01L21/8238 , H01L23/58
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。
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公开(公告)号：US20080302559A1
公开(公告)日：2008-12-11
申请号：US12009581
申请日：2008-01-18
Applicant: Glenn Joseph Leedy
Inventor： Glenn Joseph Leedy
IPC: H05K1/00
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。
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公开(公告)号：US07064033B2
公开(公告)日：2006-06-20
申请号：US10880044
申请日：2004-06-29
Applicant: Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
Inventor： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
IPC: H01L21/336
CPC classification number: H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.
Abstract translation: 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并且与N型半导体衬底形成欧姆接触，形成在N型半导体衬底中的半导体元件以及在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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公开(公告)号：US20050156265A1
公开(公告)日：2005-07-21
申请号：US11042581
申请日：2005-01-24
Applicant: Glenn Leedy
Inventor： Glenn Leedy
IPC: G21K5/02 , B81B3/00 , G02F1/13 , G03F7/20 , G11C29/00 , H01L21/027 , H01L21/306 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/98 , H01L23/48 , H01L23/538 , H01L25/065 , H01L27/00 , H01L27/02 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/732 , H01L29/78 , H01L29/786 , H05G1/00 , G01R31/26 , H01L21/00 , H01L21/50
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。
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公开(公告)号：US06903417B2
公开(公告)日：2005-06-07
申请号：US10651277
申请日：2003-08-28
Applicant: Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
Inventor： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
IPC: H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L23/48 , H01L23/52
CPC classification number: H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
Abstract translation: 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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公开(公告)号：US20050082641A1
公开(公告)日：2005-04-21
申请号：US10971341
申请日：2004-10-22
Applicant: Glenn Leedy
Inventor： Glenn Leedy
IPC: G21K5/02 , B81B3/00 , G02F1/13 , G03F7/20 , G11C29/00 , H01L21/027 , H01L21/306 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/98 , H01L23/48 , H01L23/538 , H01L25/065 , H01L27/00 , H01L27/02 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/732 , H01L29/78 , H01L29/786 , H05G1/00 , H01L21/8222
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。
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公开(公告)号：US20040150068A1
公开(公告)日：2004-08-05
申请号：US10742282
申请日：2003-12-19
Applicant: Elm Technology Corporation
Inventor： Glenn Joseph Leedy
IPC: H01L029/00
CPC classification number: H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
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公开(公告)号：US20040110318A1
公开(公告)日：2004-06-10
申请号：US10725874
申请日：2003-12-02
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takahiro Oguchi
IPC: H01L021/00
CPC classification number: G01C19/5719 , B81B2201/025 , B81C1/00579 , B81C1/00587 , B81C2201/0132 , B81C2201/014 , G01P15/0802 , G01P15/125 , G01P2015/0814 , Y10S148/012 , Y10S148/135 , Y10S148/159
Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.
Abstract translation: 通过干式蚀刻中的蚀刻停止层，使用通过元件基板的贯通孔干蚀刻形成传感器元件的外力检测传感器的制造方法。
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公开(公告)号：US20040036140A1
公开(公告)日：2004-02-26
申请号：US10651277
申请日：2003-08-28
Inventor： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
IPC: H01L029/00
CPC classification number: H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
Abstract translation: 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
