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公开(公告)号:US12104280B2
公开(公告)日:2024-10-01
申请号:US17849579
申请日:2022-06-24
发明人: Thuc Hue Ly , Lingli Huang , Honglin Chen
CPC分类号: C30B29/46 , C30B25/105 , C30B25/18 , B82Y30/00
摘要: Disclosed herein is a method of producing a substrate having a wrinkle pattern of a single-layer rhenium disulfide (ReS2) nanoflakes deposited thereon. The method is characterized by using ammonium rhenium and sulfur powders as the rhenium source and the sulfur source, respectively; and with the addition of molecular sieve to control the release of the rhenium source during the deposition of ReS2, in which a single layer of ReS2 is deposited on a substrate via chemical vapor deposition. The single-layer ReS2 is then exposed to UV light to induce the formation of a wrinkle pattern.
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公开(公告)号:US20240309556A1
公开(公告)日:2024-09-19
申请号:US18603541
申请日:2024-03-13
申请人: FLOSFIA INC.
发明人: Makoto SHIMIZU , Hiroshi SHIHO , Hiroyuki ANDO , Naoyuki TSUKAMOTO , Yuji KATO
摘要: The present disclosure provides a film formation method having an excellent mass productivity.
In the film formation method, at least one of a metal complex having two or more different ligands, and a metal complex having same ligands and substituents is used.-
公开(公告)号:US20240304676A1
公开(公告)日:2024-09-12
申请号:US18271447
申请日:2022-01-06
发明人: Takaya MIYASE , Hideyuki HISANABE
CPC分类号: H01L29/32 , C30B25/183 , C30B25/20 , C30B29/36 , H01L29/1608
摘要: A silicon carbide epitaxial layer includes a buffer layer in contact with the silicon carbide substrate, a transition layer disposed on the buffer layer, and a drift layer disposed on the transition layer. An area density of the first defect is a first area density, and an area density of the second defect is a second area density, the first area density is 0.03/cm2 or more, and a value obtained by dividing the second area density by a sum of the first area density and the second area density is less than 2.91%. The first defect, as viewed perpendicularly to the main surface, is shaped to bifurcate from a first origin. No recessed groove is present on an imaginary line segment connecting both ends of the first defect.
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公开(公告)号:US20240301584A1
公开(公告)日:2024-09-12
申请号:US18667515
申请日:2024-05-17
发明人: Christopher S. OLSEN , Theresa K. GUARINI , Jeffrey TOBIN , Lara HAWRYLCHAK , Peter STONE , Chi Wei LO , Saurabh CHOPRA
CPC分类号: C30B25/186 , C30B29/06 , C30B29/08
摘要: A process for cleaning a substrate includes removing carbon containing contaminants from a native oxide layer on a surface of a substrate by performing a reducing process using a hydrogen containing plasma, and after removing carbon containing contaminants, removing the native oxide layer from the substrate by performing an etch process using a fluorine containing plasma.
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公开(公告)号:US20240282646A1
公开(公告)日:2024-08-22
申请号:US18465011
申请日:2023-09-11
发明人: Jiaqi HONG , Jun TAN , Qiang YAN
IPC分类号: H01L21/66 , C30B25/16 , C30B25/18 , C30B29/06 , C30B29/52 , C30B29/68 , G01B11/06 , H01L21/02
CPC分类号: H01L22/26 , C30B25/16 , C30B25/186 , C30B29/06 , C30B29/52 , C30B29/68 , G01B11/06 , H01L21/02057 , H01L21/0245 , H01L21/02502 , H01L21/02532
摘要: The present application discloses a method for measuring thickness of a silicon epitaxial layer, including: step 1: performing epitaxial growth to grow a first semiconductor material layer made of a material optically distinguishable from a silicon layer on a surface of a first wafer composed of a first silicon substrate; step 2: performing epitaxial growth to grow a first silicon epitaxial layer; step 3: measuring the thickness of silicon to obtain the first thickness of the first silicon epitaxial layer; step 4: performing epitaxial growth on a surface of the first silicon epitaxial layer to form a second silicon epitaxial layer; step 5: measuring the thickness of silicon to obtain the superposed thickness of the first silicon epitaxial layer and the second silicon epitaxial layer, and subtracting the first thickness from the superposed thickness to obtain the thickness of the silicon epitaxial layer.
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公开(公告)号:US20240279842A1
公开(公告)日:2024-08-22
申请号:US18567210
申请日:2022-05-24
申请人: SHIN-ETSU CHEMICAL CO., LTD. , NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
CPC分类号: C30B29/04 , C01B32/26 , C30B25/08 , C30B25/105 , C30B25/183 , C01P2002/72
摘要: A method for manufacturing a diamond substrate, the method being a method for producing a (111) oriented diamond crystal on an underlying substrate by epitaxial growth using hydrogen-diluted methane as a main source gas by a microwave plasma CVD method, a direct current plasma CVD method, a hot-filament CVD method, or an arc discharge plasma jet CVD method, in which a growth rate is less than 3.8 μm/h. Thereby, a diamond crystal applicable to an electronic and magnetic device and a method to produce this crystal are stably provided in which the crystal with the NV axis with orientation and high-density NVC obtained by the CVD method under a predetermined condition is grown on a highly oriented (111) diamond base substrate obtained by the CVD method also under a predetermined condition.
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公开(公告)号:US20240274746A1
公开(公告)日:2024-08-15
申请号:US18566764
申请日:2022-06-06
CPC分类号: H01L31/1844 , C30B25/18 , C30B25/20 , C30B29/40 , C30B29/42 , H01L31/0735
摘要: Disclosed herein are methods for the growth of (110) GaAs solar cells by hydride vapor phase epitaxy (HVPE) as an advance towards a (110)-oriented device platform with substrate reuse via spalling. Controlled spalling offers a fracture-based path to substrate amortization, allowing device removal and substrate reuse, but the faceted surface generated in spalling of (100)-GaAs presents hurdles to direct regrowth of subsequent devices. Spalling of (110)-oriented substrates takes advantage of the natural (110) cleavage plane in zinc-blende III-V materials, eliminating this faceting.
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公开(公告)号:US12049711B2
公开(公告)日:2024-07-30
申请号:US16973706
申请日:2019-05-20
发明人: Koji Onomitsu , Kazuyuki Hirama
IPC分类号: C30B23/02 , C23C16/27 , C23C16/34 , C30B25/18 , C30B29/04 , C30B29/40 , C30B29/68 , C30B33/10
CPC分类号: C30B29/68 , C23C16/27 , C23C16/342 , C30B23/025 , C30B25/183 , C30B29/04 , C30B29/403 , C30B33/10
摘要: A material composed of an element having no catalytic action is epitaxially grown on a nickel layer to form a material layer. For example, iridium is epitaxially grown to form the material layer. Next, a cubic crystal is epitaxially grown on the material layer to form a crystal layer, and a laminate structure including the material layer and the crystal layer is patterned to form a vibrator shape part. The thickness of the material layer is controlled within a range in which lattice relaxation is not complete.
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9.
公开(公告)号:US20240250115A1
公开(公告)日:2024-07-25
申请号:US18287939
申请日:2022-03-30
CPC分类号: H01L29/04 , C30B25/16 , C30B25/18 , C30B29/16 , H01L21/0242 , H01L21/0243 , H01L21/02565 , H01L21/0262
摘要: A laminated structure including, a ground substrate with a crystalline oxide film containing gallium oxide as a main component and a root-mean-square of a roughness on a surface of the crystalline oxide film is 0.2 μm or less. A diameter of the ground substrate is 50 mm or more and TTV of the ground substrate is 30 μm or less.
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公开(公告)号:US20240234544A1
公开(公告)日:2024-07-11
申请号:US18538267
申请日:2023-12-13
发明人: Sai Hooi Yeong , Benjamin Colombeau , Liu Jiang , El Mehdi Bazizi , Byeong Chan Lee , Balasubramanian Pranatharthiharan
IPC分类号: H01L29/66 , C23C16/02 , C23C16/04 , C23C16/32 , C23C16/40 , C23C16/56 , C30B25/04 , C30B25/18 , C30B29/06 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号: H01L29/66553 , C23C16/0227 , C23C16/045 , C23C16/325 , C23C16/401 , C23C16/56 , C30B25/04 , C30B25/186 , C30B29/06 , H01L29/0673 , H01L29/41775 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.
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