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公开(公告)号：US20250060403A1
公开(公告)日：2025-02-20
申请号：US18235267
申请日：2023-08-17
Applicant: National Yang Ming Chiao Tung University
Inventor： Rustam Kumar , Tian-Li WU
Abstract: A power device threshold voltage measurement circuit and its operation method thereof are provided. The measurement circuit includes a switch component, a device under test, a common source capacitor and a decoupling capacitor. The switch component and the device under test forms a half bridge circuit and the common source capacitor is in series connected at the source of the device under test. The device under test is connected as a lower switch of the half bridge circuit and the decoupling capacitor is connected between the device under test and the common source capacitor. By applying an OFF-state stress mode and a measurement mode successively afterwards, a threshold voltage of the device under test is obtained. And the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.
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公开(公告)号：US12228603B2
公开(公告)日：2025-02-18
申请号：US18427064
申请日：2024-01-30
Applicant: SEMIGHT INSTRUMENTS CO., LTD
Inventor： Zhe Lian , Pengsong Xu , Jianjun Huang , Haiyang Hu
IPC: G01R31/26
Abstract: A wafer-level semiconductor high-voltage reliability test fixture is provided. The test fixture includes: a first insulation plate, a first circuit board, and a second insulation plate. A target object is disposed between the first circuit board and the second insulation plate. A side of the first circuit board facing the target object is provided with a probe holder including probes. The first circuit board is connected to the target object through the probes such that a high-voltage electrical signal is transmitted to the target object when the high-voltage electrical signal is applied to the first circuit board. The first insulation plate and the second insulation plate isolate the high-voltage electrical signal from the outside world, and the probes also transmit test electrical signals to the target object and transmit feedback signals to the first circuit board when the test electrical signals are applied to the first circuit board.
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公开(公告)号：US12228598B2
公开(公告)日：2025-02-18
申请号：US17813633
申请日：2022-07-20
Inventor： Mao-Hsuan Chou , Ruey-Bin Sheen , Chih-Hsien Chang
Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is β times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.
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公开(公告)号：US12210055B2
公开(公告)日：2025-01-28
申请号：US18337470
申请日：2023-06-20
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang
Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
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公开(公告)号：US20250012849A1
公开(公告)日：2025-01-09
申请号：US18710303
申请日：2022-11-17
Applicant: ams-OSRAM International GmbH
Inventor： Siegfried Herrmann
Abstract: In an embodiment a wafer includes a plurality of optoelectronic components and means for testing at least one of the optoelectronic components for at least one parameter, wherein the plurality of optoelectronic components includes at least one light-emitting layer, which is arranged between an insulating layer and a light emission layer, wherein the insulating layer of at least one optoelectronic component comprises a first contact and a second contact arranged on the light emission layer of the at least one optoelectronic component, and wherein the second contact is arranged outside a light emission surface of the at least one optoelectronic component.
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Patent Agency Ranking
公开(公告)号：US20250012843A1
公开(公告)日：2025-01-09
申请号：US18891071
申请日：2024-09-20
Applicant: DENSO CORPORATION
Inventor： Akira TOKUMASU
Abstract: A short-circuit detecting circuit is applied for a DESAT detecting circuit provided with a diode of which the cathode is connected to a high potential side terminal of an insulated gate type semiconductor element and a capacitor of which the first end is connected to an anode side of the diode and a second end is connected to a low potential side of the semiconductor switching element, detecting a short-circuit of the semiconductor element. The short-circuit detecting circuit includes a gate voltage terminal though which a gate voltage of the semiconductor is acquired; a DESAT voltage terminal through which a desaturation voltage corresponding to a capacitor voltage of the capacitor is acquired; and a determination circuit that detects, based on (i) the gate voltage exceeding a predetermined gate voltage threshold and (ii) the DESAT voltage exceeding a predetermined DESAT voltage threshold, a short-circuit of the semiconductor switching element.
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公开(公告)号：US20250004037A1
公开(公告)日：2025-01-02
申请号：US18882802
申请日：2024-09-12
Applicant: TRUMPF Photonic Components GmbH
Inventor： Sven Bader
Abstract: A method for providing a calibration number for optimizing an evaluation of a detection signal obtained from a self-mixing interference of a VCSEL includes measuring a threshold current at which the VCSEL starts to emit a laser light, measuring a working current at a specified power value of the laser light, measuring a working voltage at a specified first electric current value, and determining the calibration number by using a processor based on the threshold current, the working current, and the working voltage.
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公开(公告)号：US12181511B2
公开(公告)日：2024-12-31
申请号：US17899274
申请日：2022-08-30
Applicant: Saimeite Technology Co., Ltd.
Inventor： Lincheng Han
IPC: G01R31/26
Abstract: The present disclosure provides a method and a device for testing a wafer, an electronic device, and storage medium, wherein the method includes: obtaining plural test sheets; dividing the wafers to be tested in the plurality of test sheets according to individual test items in the plurality of test sheets, and determining the wafers to be tested corresponding to individual divided units; determining a test sequence of the test items to be performed on each wafer to be tested, based on a test sequence condition of the test items in individual test sheets and a test condition of a testing machine corresponding to individual divided units; and testing the wafer to be tested, according to the test sequence of the test items to be performed on any of the wafers to be tested.
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公开(公告)号：US12174239B2
公开(公告)日：2024-12-24
申请号：US17520567
申请日：2021-11-05
Applicant: Microsoft Technology Licensing, LLC
Inventor： Quang Thanh Tran , Judith Cutaran Aarts , John S. Hickman
IPC: G01R31/26 , G01K3/00 , G01R19/165
Abstract: Techniques are described herein that are capable of using variable voltage sources to control respective thermoelectric coolers independently in a thermal testing environment. The variable voltage sources create temperature differentials between first and second opposing surfaces of the thermoelectric coolers by applying input voltages to the respective thermoelectric coolers. Heat is transferred, by first heat exchanger(s), between a fluid and respective subset(s) of the thermoelectric coolers Heat is transferred, by second heat exchanger(s), between semiconductor device(s) and the subset(s) of the thermoelectric coolers.
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公开(公告)号：US12174237B2
公开(公告)日：2024-12-24
申请号：US17961854
申请日：2022-10-07
Applicant: University of Houston System , The United States of America, as represented by the Secretary of the Navy
Inventor： Harish Krishnamoorthy , Joshua Hawke
Abstract: A system for monitoring a circuit, comprising a device under test, such as a power field effect transistor or capacitor, coupled to a power source and a signal source and configured to generate a power output using the signal source, a current output, a voltage output and an end of life detector coupled to the current output and the voltage output and configured to generate a first impedance as a function of the current output and the voltage output, to compare the first impedance to a second impedance and to generate an indicator if the first impedance exceeds the second impedance.
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