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    SEMICONDUCTOR FAILURE ANALYSIS DEVICE AND SEMICONDUCTOR FAILURE ANALYSIS METHOD
    1.
    发明公开
    SEMICONDUCTOR FAILURE ANALYSIS DEVICE AND SEMICONDUCTOR FAILURE ANALYSIS METHOD 审中-公开

    公开(公告)号：US20240361382A1

    公开(公告)日：2024-10-31

    申请号：US18579888

    申请日：2022-03-15

    申请人： HAMAMATSU PHOTONICS K.K.

    发明人： Masataka IKESU ,  Tomonori NAKAMURA

    IPC分类号： G01R31/311 ,  G01R31/28

    CPC分类号： G01R31/311 ,  G01R31/2879

    摘要： A semiconductor failure analysis device includes a first analysis unit that emits first irradiation light along a first path set on a first main surface of a semiconductor device, a second analysis unit that emits second irradiation light along a second path set on a second main surface that is a back side of the first main surface, an electric signal acquisition unit that receives an electric signal output from the semiconductor device irradiated with the first irradiation light and the second irradiation light, and a computer that controls the second analysis unit. A size of a first irradiation region is different from a size of a second irradiation region. The computer emits the first irradiation light and the second irradiation light while a state where the entire second irradiation region overlaps the first irradiation region is maintained.

    METHOD AND DEVICE FOR WAFER-LEVEL TESTING
    2.
    发明公开
    METHOD AND DEVICE FOR WAFER-LEVEL TESTING 审中-公开

    公开(公告)号：US20240361380A1

    公开(公告)日：2024-10-31

    申请号：US18765343

    申请日：2024-07-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： JUN HE ,  YU-TING LIN ,  WEI-HSUN LIN ,  YUNG-LIANG KUO ,  YINLUNG LU

    IPC分类号： G01R31/28 ,  G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/2642 ,  G01R31/2886

    摘要： The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.

    Two-Step Charge-Based Capacitor Measurement
    3.
    发明公开
    Two-Step Charge-Based Capacitor Measurement 审中-公开

    公开(公告)号：US20240361370A1

    公开(公告)日：2024-10-31

    申请号：US18767126

    申请日：2024-07-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tai-Yi Chen ,  Chung-Chieh Yang ,  Chih-Chiang Chang ,  Chung-Ting Lu

    IPC分类号： G01R27/26 ,  G01R31/26 ,  G01R31/28 ,  H03K19/094

    CPC分类号： G01R27/2605 ,  G01R31/2639 ,  G01R31/2841 ,  H03K19/094

    摘要： Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

    Module substrate for semiconductor module, semiconductor module and test socket for testing the same
    4.
    发明授权
    Module substrate for semiconductor module, semiconductor module and test socket for testing the same 有权

    公开(公告)号：US12130306B2

    公开(公告)日：2024-10-29

    申请号：US17884661

    申请日：2022-08-10

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kwangkyu Bang ,  Kiljoong Yun ,  Yun Chang ,  Jaegyu Choi

    IPC分类号： G01R1/04 ,  G01R31/28

    CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R31/2863 ,  G01R31/2884

    摘要： A module substrate for a semiconductor module includes: a wiring substrate having an upper surface and a lower surface opposite to the upper surface, wherein the wiring substrate includes a circuit wiring and a plurality of via holes extending from the upper surface to the lower surface in a thickness direction; a plurality of test terminals respectively provided on the via holes and electrically connected to the circuit wiring, and a fastening thin film provided on the wiring substrate and covering the via holes, wherein the fastening thin film has a predetermined thickness such that a portion of the fastening thin film is penetrated when an interface is pin is inserted into the portion of the fastening thin film through the via hole from the upper surface, and the portion of the penetrated fastening thin film holds the penetrating interface inspection pin.

    Probe-holder support and corresponding probes with facilitated mounting
    5.
    发明公开
    Probe-holder support and corresponding probes with facilitated mounting 审中-公开

    公开(公告)号：US20240353481A1

    公开(公告)日：2024-10-24

    申请号：US18762224

    申请日：2024-07-02

    申请人： Microtest S.p.A.

    发明人： Giuseppe Amelio

    IPC分类号： G01R31/28 ,  G01R1/067 ,  G01R31/26

    CPC分类号： G01R31/2887 ,  G01R1/06705 ,  G01R31/2601

    摘要： A contact probe for electronic tests includes an upper part having an end portion for contacting a first electronic component; a lower part having an end for contacting a second electronic component; and an elongated and deformable central body interposed between the upper and lower parts. The lower part has an enlarged head with a lower surface intended to rest at least partially onto a horizontal surface, the lower surface having an inclination angle from the horizontal surface onto which it rests when the probe is unbuckled and, when the probe is buckled, it can assume a position in which the lower surface moves to rest entirely onto the horizontal surface, thereby eliminating the inclination angle.

    ON-CHIP FAULT DETECTION DUE TO MALFUNCTIONS ON CHIP PINS
    7.
    发明公开
    ON-CHIP FAULT DETECTION DUE TO MALFUNCTIONS ON CHIP PINS 审中-公开

    公开(公告)号：US20240353479A1

    公开(公告)日：2024-10-24

    申请号：US18458382

    申请日：2023-08-30

    申请人： NXP USA, Inc.

    发明人： Kumar Abhishek ,  Neha Srivastava ,  Vivek Kumar Yadav ,  Sanjaykumar Hansrajbhai Kakasaniya ,  Vikram Joshi

    IPC分类号： G01R31/28 ,  H03K3/037

    CPC分类号： G01R31/2884 ,  H03K3/037 ,  H03K19/20

    摘要： A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.

    SEMICONDUCTOR TESTING DEVICE AND METHOD OF OPERATING THE SAME
    8.
    发明公开
    SEMICONDUCTOR TESTING DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20240353474A1

    公开(公告)日：2024-10-24

    申请号：US18758635

    申请日：2024-06-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kong-Beng THEI ,  Jung-Hui KAO ,  Jing-Jung HUANG ,  Fu-Hsiung YANG

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2831 ,  G01R31/2884

    摘要： A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.

    Loopback testing of integrated circuits
    9.
    发明授权
    Loopback testing of integrated circuits 有权

    公开(公告)号：US12123908B1

    公开(公告)日：2024-10-22

    申请号：US18367333

    申请日：2023-09-12

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Shai Cohen ,  Evelyn Landman

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3177

    CPC分类号： G01R31/2896 ,  G01R31/31727 ,  G01R31/3177

    摘要： Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.