PUSH-PULL LOW-DROPOUT (LDO) VOLTAGE REGULATOR

    公开(公告)号:US20240402744A1

    公开(公告)日:2024-12-05

    申请号:US18325632

    申请日:2023-05-30

    Abstract: A push-pull Low Dropout (LDO) voltage regulator is provided. An instantaneous output voltage of the push-pull LDO voltage regulator is compared with a first reference voltage and a first output based on comparing the first reference voltage with the instantaneous output voltage is provided. The instantaneous output voltage of the push-pull LDO voltage regulator is compared with a second reference voltage and a second output based on comparing the instantaneous output voltage with the second reference voltage is provided. One or more bi-directional drivers of a plurality of bi-directional drivers of the push-pull LDO voltage regulator are driven based on the first output and the second output. The plurality of bi-directional drives provide the predetermined output voltage.

    MULTI-PORT DRIVING AND SENSING CIRCUIT
    4.
    发明公开

    公开(公告)号:US20240241532A1

    公开(公告)日:2024-07-18

    申请号:US18403648

    申请日:2024-01-03

    CPC classification number: G05F1/575 G05F1/595

    Abstract: A multi-port driving and sensing circuit is disclosed and provided for multi-load application. The multi-port driving and sensing circuit has a plurality of bridge switching unit and a controlling unit. A first and second upper switches of each bridge switching unit are commonly connected to a driving voltage terminal, and a first and second lower switches are commonly connected to a reference voltage terminal. When the controlling unit executes a sensing procedure, the first and second upper switches of each bridge switching unit disconnect to the driving voltage terminal and a sensing voltage signal of a load connected to each bridge switching unit is read through a signal reading unit. Therefore, when the sensing voltage signal of the load connected to one of the bridge switching units is read, the sensing voltage signal is not interfered by other sensing voltage signals of the load connected to other bridge switching units.

    Semiconductor device, electronic device, and artificial satellite

    公开(公告)号:US11899478B2

    公开(公告)日:2024-02-13

    申请号:US17298695

    申请日:2019-11-18

    CPC classification number: G05F1/56 G05F1/595

    Abstract: A low-power semiconductor device is provided. A retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of a source and a drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to a gate of the output transistor. A node to which the other of the source and the drain of the retention transistor and the gate of the output transistor are electrically connected is a retention node. When the retention transistor is in an on state, a potential corresponding to a potential output from the control circuit is written to the retention node. Then, when the retention transistor is in an off state, the potential of the retention node is retained. Thus, a gate potential of the output transistor can be kept at a constant value even when the control circuit is off. Accordingly, even when the control circuit is off, a constant potential can be continuously output from one of a source and a drain of the output transistor, for example.

    VOLTAGE REFERENCE CIRCUIT AND A POWER MANAGEMENT UNIT

    公开(公告)号:US20230333584A1

    公开(公告)日:2023-10-19

    申请号:US18135904

    申请日:2023-04-18

    Applicant: IMEC VZW

    CPC classification number: G05F1/595 G05F1/575 A61B5/37

    Abstract: A voltage reference circuit comprises: first transistor, second transistor, first regulating transistor, and second regulating transistor arranged in a stacked connection, wherein first voltage is provided at first node between first and second transistor, second voltage is provided at second node between second transistor and first regulating transistor, third voltage is provided at third node between first and second regulating transistor; wherein first regulating transistor and second regulating transistor are connected to first node and second node, respectively, for compensating changes in first voltage and second voltage, respectively, to maintain stable voltage levels; wherein voltage reference circuit outputs at least one of the first, second or third voltage as a reference voltage.

    Internal voltage generation circuit

    公开(公告)号:US11755045B1

    公开(公告)日:2023-09-12

    申请号:US17882256

    申请日:2022-08-05

    Applicant: SK hynix Inc.

    CPC classification number: G05F1/465 G05F1/595

    Abstract: An internal voltage generation circuit includes a shifting source voltage generation circuit configured to generate a shifting source voltage having a voltage level that falls as a voltage level of a power supply voltage rises during a period when the power supply voltage is lower than a preset voltage level. The internal voltage generation circuit also includes an internal voltage regulator configured to generate a driving signal through a level shifting operation that is performed according to the shifting source voltage received when driving an internal voltage and configured to drive the internal voltage based on the driving signal.

    High voltage logic circuit
    10.
    发明授权

    公开(公告)号:US11411000B2

    公开(公告)日:2022-08-09

    申请号:US17140806

    申请日:2021-01-04

    Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

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